使用脚本对quartus工程进行全自动化仿真

本文介绍使用脚本对quartus工程进行全自动化仿真的方法，以下方法针对quartus pro版本。

设置EDA工具

在 Quartus 软件里点击Assignments -> Settings ->EDA Tool Settings。在Tool name中选择ModelSim-Intel FPGA。

产生仿真模板

编译工程后，点击 Tools -> Generate Simulator Setup Script for IP，在输出路径设置为mentor文件夹，产生模板文件 msim_setup.tcl。

产生用于仿真的 do 文件

根据仿真模板产生用于仿真的 do 文件。打开模板文件 msim_setup.tcl，新建一个文本文件mentor_example.do。将 msim_setup.tcl 中，把 TOPLEVEL TEMPLATE – BEGIN 到 TOP-LEVEL TEMPLATE – END 之间的内容，拷贝到 mentor_example.do 文件中。

# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog <compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run -a
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END

修改mentor_example.do 文件

修改后

# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
 set QSYS_SIMDIR ../
# #
# # Source the generated IP simulation script.
 source $QSYS_SIMDIR/mentor/msim_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
 dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
 com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
 vlog -work work ../../src/demo.v
 vlog -work work ../testbench.v
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
 set TOP_LEVEL_NAME demo_vlg_tst
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
 elab
# #
# # Run the simulation.
 add wave *
 view structure
 view signals
 run -all
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END

需要注意的地方

• testbench为测试平台，是.v文件。
• demo_vlg_tst为testbench.v中module名。
• vlog -work work中添加文件路径。

仿真

• 打开ModelSim - Intel FPGA starter Edition
• File->change directory，指向 mentor_example.do 所在的文件夹
• 在 transcript 里输入do mentor_example.do，回车

自动化仿真

新建批量化处理文件，自动打开modelsim进行仿真，新建batch_sim.bat文件，文件与mentor_example.do在同一目录下，batch_sim.bat内容如下：

vsim -do mentor_example.do

双击batch_sim.bat，不用打开modelsim，直接进行仿真。