8086虚拟存储器_8086微处理器中的存储器组织

8086虚拟存储器

There are 20 address lines in the 8086 microprocessor. This gives us 220 different memory locations. Hence the total size is 220 Bytes (as each memory location is Byte Addressable, i.e. one byte of data can be stored at every single location), which is equal to 1MB.

8086微处理器中有20条地址线。 这给了我们220个不同的内存位置。 因此，总大小为220字节(因为每个存储位置都是可字节寻址的，即每个字节中可以存储一个字节的数据)，等于1MB。

Even the memory is byte-addressable, yet the 8086 microprocessor an easily handle up to 16 bits of data at a time through its 16 data lines. So, to organize the memory efficiently, the entire memory in 8086 is divided into two memory banks: odd bank and the even bank.

即使存储器是可字节寻址的，但8086微处理器仍可通过其16条数据线轻松一次处理多达16位数据。 因此，为了有效地组织存储器，8086中的整个存储器分为两个存储体：奇数存储体和偶数存储体。

The way in which data is read or written is decided by the value of BHE, and the last address bit, that is the A0 line. It is done in the following way:

数据的读取或写入方式取决于BHE的值以及最后一个地址位，即A0线。 它是通过以下方式完成的：

BHE'	A0	Operation performed on memory
0	0	16 bits of data will be read or written into the memory
0	1	8 bits of data will be read/written into the odd memory bank
1	0	8 bits of data will be read/written into the even memory bank
1	1	No operation is performed

BHE'	A0	在内存上执行的操作
0	0	16位数据将被读取或写入存储器
0	1个	8位数据将被读/写到奇数存储区
1个	0	8位数据将被读/写到偶数存储库
1个	1个	不执行任何操作

To read or write 8 bits of data, it would require only 1 CPU cycle, no matter the data is stored in any of the memory banks, but to read or write 16 bits of data, the BIU of the 8086 may require either 1 or 2 memory cycles depending upon whether the lower byte of word is located at even or odd memory address.

要读取或写入8位数据，无论数据存储在任何存储体中，都只需要1个CPU周期，但是要读取或写入16位数据，8086的BIU可能需要1个或2个字节。 2个存储周期取决于字的低字节位于偶数还是奇数存储地址。

1. If the lower byte of the word is stored at even memory bank and the upper byte is stored at odd memory bank then the CPU will require only 1 memory cycle. So, it is better to store data in this way.

   如果字的低字节存储在偶数存储库中，而高字节存储在奇数存储库中，则CPU仅需要1个存储周期。 因此，最好以这种方式存储数据。

2. If the lower byte of the word is located at an odd memory address, then the CPU will require 2 memory cycles. The first memory cycle is required for accessing the lower byte of the word through the higher data bus, i.e. D15 to D8, and the second memory cycle is required for accessing the upper byte of the word through the lower data bus, i.e. D7 to D0.

   如果该字的低字节位于奇数个存储器地址，则CPU将需要2个存储器周期。 通过较高的数据总线(即D15至D8)访问字的低字节需要第一个存储周期，而通过较低的数据总线(D7至D0)访问字的高字节需要第二个存储周期。

翻译自: https://www.includehelp.com/embedded-system/memory-organization-in-the-8086-microprocessor.aspx

8086虚拟存储器