ERROR:PhysDesignRules:2449 - The computed value for the VCO operating frequency of PLL_ADV instance

ERROR:PhysDesignRules:2449 - The computed value for the VCO operating frequency
   of PLL_ADV instance
   cpu_sys_i/clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV
   _inst is calculated to be 1300.000000 MHz. This falls above the operating
   range of the PLL VCO frequency for this device of 400.000000 - 1080.000000
   MHz. Please adjust either the input frequency CLKINx_PERIOD, multiplication
   factor CLKFBOUT_MULT or the division factor DIVCLK_DIVIDE, in order to
   achieve a VCO frequency within the rated operating range for this device.
ERROR:Pack:1642 - Errors in physical DRC.

ISE调用MCB_DDR3模块综合产生ERROR，原因：时钟频率配置错误，频率超出器件工作频率；修改方法：

使用xilinx IP核生成器生成MIG IP核，得到顶层文件，根据器件重新配置如下参数：

时钟分频系数原为：

   constant C3_CLKOUT0_DIVIDE       : integer := 1;

   constant C3_CLKOUT1_DIVIDE       : integer := 1;

   constant C3_CLKOUT2_DIVIDE       : integer := 16 ;

   constant C3_CLKOUT3_DIVIDE       : integer := 8;

   constant C3_CLKFBOUT_MULT        : integer := 2 ;

   constant C3_DIVCLK_DIVIDE        : integer := 1;

   constant C3_INCLK_PERIOD         : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));

更改为如下：

   constant C3_CLKOUT0_DIVIDE       : integer := 1;

   constant C3_CLKOUT1_DIVIDE       : integer := 1;

   constant C3_CLKOUT2_DIVIDE       : integer := 4 ;

   constant C3_CLKOUT3_DIVIDE       : integer := 8;

   constant C3_CLKFBOUT_MULT        : integer := 8 ;

   constant C3_DIVCLK_DIVIDE        : integer := 1;

   constant C3_INCLK_PERIOD         : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));

For a x64 bit User interface:

The user clock should be set at or above (16/64) * 400 MHz = 100 MHz