utopia

The Level 1 and Level 2 Utopia specifications describe the data path between a Physical

layer device and an ATM layer device, utilizing a 8-bit or 16-bit data path, catering for

data rates of up to 800 Mb/s. The control of the data exchange is performed using celllevel handshaking.

The Utopia Level 3 specification has been generated to match the development in

Physical layer interface standards towards higher interface rates (1.2 Gb/s, 2.4 Gb/s). The

data path described in this specification allows for data transport at rates of up to

3.2 Gb/s.

The description of AC characteristics features the nominal bus bandwidth and the

clocking scheme:

1) 32-bit, 16-bit or 8-bit data path

2) The nominal bus bandwidth of 3.2 Gb/s (32-bit mode), 1.6 Gb/s (16-bit mode) or

800 Mb/s (8-bit mode)

3) Single-edged clocking of data and control/status signals

Vdd = 3.3V nominal.

The Utopia Level 3 interface as specified in this document is NOT backwards compatible

with the Level 1 and Level 2 interfaces. Both data bus width and handshaking

mechanisms have changed, making direct interfacing between a Utopia Level 3 interface

and a Level 1 or 2 interface not possible.

2.2.1 Interface speed

The interface speed will be increased with respect to previous Utopia specifications in

order to satisfy the bandwidth requirements. The actual required speed depends on Utopia

cell size. Timing parameters are specified at 104 MHz.

2.2.2 Data Path

A 32-bit data path is introduced and is intended for up to 3.2 Gb/s operation. The 16-bit

data path is intended for operation of up to 1.6 Gb/s. The 8-bit data path is intended for

operation of up to 800 Mb/s.

2.2.3 P hysical topology

The physical topology of the Utopia Level 3 interface is as a point-to-point connection.

The implementation of this topology uses either a single 32-bit data path, a single 16-bit

data path or a single 8-bit data path connecting a single ATM layer device with a single

PHY layer device.

2.2.4 MPHY operation

This defines the operation of the interface with multiple PHY ports. This specification

only provides for MPHY operation when these ports are implemented in a single Multiport

PHY device.

2.2.5 Cell Transfer Burst mode

Once the transport of a cell has started, a complete cell will be transmitted across the

Utopia Level 3 interface. It is not possible to stall the transfer of a cell and all

octets/words will have to be transferred consecutively.

2.4.1 Capabilities

The Utopia Level 3 Interface is capable of full-duplex bi-directional transmission of

ATM cells between an ATM layer device (ATM) and a Physical layer device (PHY).

 

The basic reference model for the Utopia interface is given in Figure 2.1. This shows the

information streams between the ATM layer device and the Physical layer device.

Transmit data flows from ATM to PHY and Receive data flows from PHY to ATM. Both

data streams have control for handshaking.

2.6 Device Capabilities

The Utopia Level 3 interface specifies a 8-bit, 16-bit or 32-bit data path operating at

frequencies of up to 104 MHz. The format of the information transferred across this

interface is defined as 52- or 56-octet cells for the 32-bit data path, 52- or 54-octet cells

for the 16-bit data path and 52- or 53-octets for the 8-bit data path.

Only the 52- and 56-octet cell formats are defined in this specification and are as shown

in Table 2.1 & Table 2.2. Support for the 52-octet cell format is required (R). Support for

the 56-octet cell format is optional (O). Note that in the 52-octet format there is no field

for the transport of the HEC octet. However, transport of the HEC is not required, as this

is a part of Physical layer functionality. When transferring the HEC in the 56-octet cell

format the HEC shall be transferred in the first User Defined Field (UDF1). Transfer of

56-octet cells must support the bandwidth requirements indicated in 2.5.

2.8 Decode-Response Timing

A device responds in two clock cycles after the initiating signal is sent across the

interface. This deviates from Utopia Level 2 but relaxes timing constraints imposed on

the responding device. The intent of this requirement is to have both input and output

signals registered.

3. Single PHY Interface

This section describes the operation of the Utopia Level 3 in Single PHY interface mode.

In this configuration one ATM layer port and one PHY layer port will be connected.

3.1 Signals

Since this mode of operation only provides functionality to interface a single ATM port

with a single PHY port the handshake requirements are minimal.

3.1.1 Transmit Interface

This section defines the signals required for the Transmit interface. These signals are the

same signals as described in the Utopia Level 1 and 2 specifications, but are given for

completeness.

The following signals are defined as required (R) for the Transmit interface:

TxClav[0]

Cell Buffer Available. To indicate that space for at least one cell is available in the

PHY transmit cell buffer.

TxEnb*

Transmit Enable. The assertion of TxEnb* is coincident with the start of the cell

transfer. TxEnb* is used for address selection in Multi-PHY mode during the last

clock cycle before it is asserted.

TxSOC

Transmit Start Of Cell. Active high signal asserted by the ATM layer to indicate

the start of cell position. TxSOC is only asserted during the first clock cycle of the

data transfer.

TxData[7:0]/TxData[15:0]/TxData[31:0]

The data path for Transmit data, from ATM to PHY. In the 32-bit data path,

TxData[31] is the MSB, TxData[0] is the LSB. In the 16-bit data path, TxData[15]

is the MSB, TxData[0] is the LSB. Similarly, in the 8-bit data path, TxData[7] is

the MSB and TxData[0] is the LSB.

TxClk

Transmit Clock, an input to both the ATM layer device and the PHY device. Used

to clock the transmit control signals and data.

The following signal is defined as optional (O) for the Transmit interface:

TxPrty（optional）

Data path parity. The TxPrty parity bit serves as the odd parity bit over

TxData[7:0]/TxData[15:0]/TxData[31:0].

3.1.2 Receive Interface

This section defines the signals required for the Receive interface. These signals are the

same signals as described in the Utopia Level 1 and 2 specifications, but are given for

completeness.

The following signals are defined as required (R) for the Receive interface:

RxClav[0]

Cell Available. To indicate that at least one cell is available in the PHY receive

cell buffer.

RxEnb*

Receive Enable. Active low signal asserted by the ATM layer device to initiate a

cell transfer. RxEnb* is used for address selection in Multi-PHY mode during the

last clock cycle before it is asserted.

RxSOC

Receive Start Of Cell. Active high signal asserted by the PHY layer to indicate the

start of cell position. RxSOC is only asserted during the first clock cycle of the

data transfer.

RxData[7:0]/RxData[15:0]/RxData[31:0]

The data path for Receive data, from PHY to ATM. In the 32-bit data path,

RxData[31] is the MSB, RxData[0] is the LSB. In the 16-bit data path,

RxData[15] is the MSB, RxData[0] is the LSB. Similarly, in the 8-bit data path,

RxData[7] is the MSB and RxData[0] is the LSB.

RxClk

Receive Clock, an input to both the ATM layer device and the PHY device. Used

to clock the receive control signals and data.

The following signal is defined as optional (O) for the Receive interface:

RxPrty（optional）

Data path parity. The RxPrty parity bit serves as the odd parity bit over

RxData[7:0]/RxData[15:0]/RxData[31:0].

3.2 Direct Status Indication

The Single PHY mode of operation only uses a single TxClav and RxClav signal and no

address information, since there is only 1 port to receive cell data from or send cell data

to. The transfer of a cell, once started, cannot be stalled or interrupted. RxEnb* and

TxEnb* must be held low until required to pause the transfer of the next cell.

3.2.1 Transmit Operation

The ATM layer device can send a cell to a PHY port only when the PHY port has

indicated to the ATM layer device that it is ready to receive at least one cell. The PHY

device will indicate this by asserting the Transmit Cell Buffer Available (TxClav). The

TxClav signal is not applicable on the first cycle after Start of Cell because of the 2 clock

cycle decode-response timing. Thereafter the PHY device will deassert TxClav unless it

can accept at least 1 cell (after the currently transferred cell) from the ATM layer device.

Once the TxClav has been asserted, it will have to stay asserted until the clock edge after

assertion of the next Start of Cell (SOC).

Figure 3.1 shows the case in which cells are transferred back-to-back, utilizing the full

bandwidth of the bus

 Figure 3.2 shows an example where the PHY indicates on clock edge 4 that it can accept

another cell but the ATM layer device does not have a cell ready for transfer. When

ready, the ATM layer will assert the TxSOC and start transmission of the cell

simultaneously (clock cycle n).

 In Figure 3.3 the PHY indicates that it has no space available for a complete cell by

deasserting the TxClav. In response to this, the ATM layer will hold off the transmission

of the next cell (even if it has a cell available for transmission). Once TxClav is asserted

by the PHY and the ATM device has a cell available for transfer, TxSOC will be asserted

and transfer takes place.

  3.2.2 Receive Operation

The PHY layer device can send a cell to a ATM port only when PHY port has indicated

that it has at least one complete ATM cell available and when the ATM port has indicated

to the PHY layer device that it is ready to receive a cell. The ATM device will indicate

this by asserting the RxEnb* in response to a Receive Cell Available (RxClav) signal

from the PHY device. During the transfer of a cell the status of the RxClav signal

indicates the availability of a subsequent cell. The ATM device must deassert RxEnb*

two cycles before the end of the cell transfer, unless a back-to-back transfer is intended.

The RxClav must be deasserted coincident with RxSOC if the PHY has no subsequent

cell available. Once the RxClav has been asserted, it will have to stay asserted until the

next Start of Cell (SOC) is asserted.

Figure 3.4 shows the case in which cells are transferred back-to-back by keeping RxEnb*

asserted at the next to the last cycle of the transfer, utilizing the full bandwidth of the bus.

 Figure 3.5 shows an example where the PHY layer device indicates on clock edge 4 or

before that it has another complete cell available but the ATM layer device does not have

space available to receive this cell. To indicate this, the ATM layer deasserts RxEnb*

until it has space available for a complete cell. The timing of the RxEnb* signal is

pipelined, which means that the response of the PHY port is two clock cycles after the

RxEnb* is asserted or deasserted.

 In Figure 3.6 the PHY indicates that it does not have a complete cell available for transfer

across the Utopia Level 3 interface by deasserting the RxClav. In response to this, the

ATM layer device will deassert the RxEnb*. Once RxClav is asserted by the PHY and the

ATM device has space available for a complete cell, the PHY will be selected by the

ATM layer device (RxEnb* asserted) and transfer takes place. The PHY layer device will

place the cell data on the RxData bus two clock cycles after the assertion of the RxEnb*.

 4. Data Path Operation – MPHY mode

This section describes the operation of the Utopia Level 3 in MPHY interface mode. In

this configuration one ATM layer port and multiple PHY layer ports will be connected.

4.1 Signals

The data path in MPHY mode consists of the same signals as described in the previous

section, with the MPHY specific additional signals described below.

4.1.1 Transmit Interface

This section defines the additional signals required for the Transmit interface to operate in

MPHY mode.

The following signals are defined as required (R) for the Transmit interface operating in

MPHY mode:

TxAddr[n:0]

Transmit Address. To select the PHY port for which the transmit data is to be

destined. The address is used in both Direct Status indication mode and the Single

Clav (polling) mode. The value of n is application specific. All 2n+1 addresses are

available for use in the application as no NULL address is supported.

The following signals are defined as optional (O) for the Transmit interface operating in

MPHY mode:

TxClav[3:1]

Cell Buffer Available. To indicate that space for at least one cell is available in the

PHY transmit cell buffer. These signals are only required in Direct Status

Indication operation.

4.1.2 Receive Interface

This section defines the additional signals required for the Receive interface to operate in

MPHY mode.

The following signals are defined as required (R) for the Receive interface operating in

MPHY mode:

RxAddr[n:0]

Receive Address. To select the PHY port from which receive data is to be read.

The address is used in both Direct Status indication mode and the Single Clav

(polling) mode. The value of n is application specific. All 2n+1 addresses are

available for use in the application as no NULL address is supported.

The following signals are defined as optional (O) for the Receive interface operating in

MPHY mode:

RxClav[3:1]

Cell Available. To indicate that at least one cell is available in the PHY receive

cell buffer. These signals are only required in Direct Status Indication operation.

4.2 Direct Status Indication

When interfacing up to 4 PHY ports to a single ATM layer device, it is possible to

implement a dedicated RxClav and TxClav signal for each of the PHY ports. The mode

of operation in this scenario is called “Direct Status Indication”. The meaning and timing

of the individual TxClav and RxClav signals is as described in section 3.2, Direct Status

Indication for the Single PHY Interface.

Timing diagrams are shown in Figure 4.1 to 4.6 to illustrate the transmit and receive

timing of the signals involved in MPHY Direct Status Indication.

4.2.1 Transmit Operation

The ATM layer device can send a cell to a PHY port only when the PHY port has

indicated to the ATM layer device that it is ready to receive at least one complete cell.

The PHY device must indicate transmit cell buffer available information to the ATM

layer device. The TxClav[3:0] is not applicable on the first cycle after Start of Cell

because of the 2 clock cycle decode-response timing. Thereafter the PHY device will

deassert TxClav unless it can accept at least 1 cell (after the currently transferred cell)

from the ATM layer device. This is illustrated in Figure 4.1 by the TxClav[3:0] indicating

the status of each of the PHY transmit ports. Once the TxClav[3:0] has been asserted, it

will have to stay asserted until the clock edge after assertion of the next Start of Cell

(SOC) on that particular port.

The PHY port to which the next cell will be sent will be selected by TxAddr[n:0] during

the clock cycle before TxEnb* is asserted. This signal will be decoded by the PHY device

and the specified port will be ready to receive cell data from the ATM side as soon as the

TxEnb* is asserted.

 Back-to-back transfer of cells is possible when two cells have to be sent to the same port

and this port indicates that it can receive the second cell. In the case of back-to-back

transfer the ATM layer device does not explicitly select the PHY port and TxEnb* will

not be deasserted. The second (or subsequent) cell is transferred immediately after the

previous one and the TxSOC is asserted to indicate the start of cell. This is illustrated in

Figure 4.2.

 In Figure 4.3 the PHY indicates that none of its ports has space available for a complete

cell by deasserting the TxClav[3:0]. This causes the ATM layer to deassert the TxEnb* as

soon as the current transfer has finished (clock cycle 8). Once a TxClav is asserted by the

PHY and the ATM device has a cell available for transfer to this port, the PHY port will

be selected by the ATM layer (TxAddr[n:0] during the clock cycle before asserting

TxEnb*) and transfer is started as soon as TxEnb* is asserted (clock cycle n+1).

  4.2.2 Receive Operation

In the receive direction, the ATM layer device controls the flow of data from the PHY

device on a per cell basis. The PHY device must indicate receive cell available

information to the ATM layer device. The ATM layer device can only explicitly select (or

implicitly reselect) a PHY port for transfer of a cell when the PHY port has indicated to

the ATM layer device that it has at least one cell available. This is illustrated in Figure

4.4 by the RxClav[3:0] indicating the status of each of the PHY receive ports. The

RxClav[3:0] must be deasserted coincident with RxSOC to indicate that the

corresponding port of the PHY has no subsequent cell available. Once the RxClav[3:0]

has been asserted, it will have to stay asserted until the Start of Cell (SOC) is asserted

(clock edge 4 in Figure 4.4) on that particular port.

A valid RxAddr[n:0] during the clock cycle before asserting the RxEnb* signal will select

the PHY port which will transfer the next cell across the Utopia interface. This signal will

be decoded by the PHY device and the specified port will be ready to transfer cell data

two clock cycles after RxEnb* goes low. The ATM device must deassert RxEnb* two

cycles before the end of the cell transfer, unless a back-to-back transfer is intended. The

decode-response timing between the RxEnb* and the RxData is therefore two clock

cycles.

 Back-to-back transfer of cells is possible when the PHY layer device indicates in time

that it has another cell to be transferred from the same port and the ATM layer device can

receive this cell. In the case of back-to-back transfer the ATM layer device implicitly

reselects the PHY port by leaving the RxEnb* asserted during the next to the last cycle of

the cell transfer. The second (or subsequent) cell is transferred immediately after the

previous one and the RxSOC is asserted to indicate the start of cell. This is illustrated in

Figure 4.5.

In Figure 4.6 the PHY indicates that none of its ports has a complete cell available for

transfer by deasserting all RxClav signals. As a response to this, the ATM layer will

deassert the RxEnb* to indicate that no cell transfer will take place after the current

transfer is completed. Once a RxClav is asserted by the PHY and the ATM device has

space available to receive a cell, the PHY port will be selected by a valid RxAddr[n:0]

during the clock cycle before asserting the RxEnb* and transfer takes place two clock

cycles after the RxEnb* has been asserted.

  4.3 Multi-PHY Operation with 1 TxClav & 1 RxClav Signal

4.3.1 General operation

The ATM layer device receives PHY port FIFO status information through the following

polling mechanism:

In the transmit direction, the ATM layer device polls by presenting the PHY’s port

address on TxAddr[n:0]. The polled PHY responds two cycles later by driving TxClav

high if the port can accept one or more complete ATM cells; TxClav is driven low

otherwise.

In the receive direction, the ATM layer device polls by presenting the PHY’s port address

on RxAddr[n:0]. The polled PHY responds two cycles later by driving RxClav high if the

port is ready to send one or more complete ATM cells to the ATM layer device; RxClav

is driven low otherwise.

4.3.2 Back-to-back polling

The single Clav mode described in this section is very similar to the mechanism described

in the Utopia Level 2 specification. However, due to the elimination of the tri-state

requirement in Utopia Level 3, it is possible to poll the PHY ports back-to-back. This

means that in both transmit and receive directions, the ATM layer device may

successively poll PHY ports on contiguous cycles.

4.3.3 Transmit Operation

The ATM layer device can send a cell to a PHY port only when the PHY port has

indicated to the ATM layer device that it is ready to receive at least one cell. The PHY

device must send transmit cell buffer available information for that port to the ATM layer

device when that port is polled, using the TxClav. Once the TxClav response for a

particular port indicates buffer availability, responses to subsequent polls of that port

must continue to indicate buffer availability until after the second cycle of the transfer of

a cell to that port.

This is illustrated in Figure 4.8 by the TxClav indicating the status of the PHY transmit

port two clock cycles after the port’s address has been selected by the ATM device. The

decode-response timing between the TxAddr and the TxClav is therefore two clock

cycles. The TxClav is not applicable on the first cycle after Start of Cell because of the 2

clock cycle decode-response timing.

TxAddr[n:0] during the clock cycle before asserting the TxEnb* signal will select the

PHY port which will receive the next cell. The PHY device will decode this signal and

the specified port will be ready to receive cell data from the ATM side at the next clock

cycle.

Back-to-back transfer of cells is possible when two cells have to be sent to the same

Multi-PHY device port and this port indicates that it can receive the second cell. In the

case of back-to-back transfer the ATM layer device implicitly reselects the PHY port by

leaving the TxEnb* asserted during the next to the last cycle of the cell transfer. The

second (or subsequent) cell is transferred immediately after the previous one and the

TxSOC is asserted to indicate the start of cell. This is illustrated in Figure 4.9.

4.3.4 Receive Operation

In the receive direction, the ATM layer device controls the flow of data from the PHY

device on a per cell basis. The ATM layer device can explicitly select (or implicitly

reselect) a PHY port for transfer of a cell only when the PHY port has indicated to the

ATM layer device that it has at least one cell available, using the RxClav.

The explicit case is illustrated in Figure 4.10 by the RxClav indicating the status of the

PHY receive port two clock cycles after the port’s address has been selected by the ATM

device. The decode-response timing between the RxAddr and the RxClav is therefore two

clock cycles. Once the RxClav response for a particular port indicates cell availability,

responses to subsequent polls of that port must continue to indicate cell availability until

the Start Of Cell (SOC) is asserted for that port.

RxAddr[n:0] during the clock cycle before asserting the RxEnb* signal will select the

PHY port which will transfer the next cell across the Utopia interface. The PHY device

will decode this signal and the specified port will be ready to transfer cell data two clock

cycles after RxEnb has gone low. The ATM device must deassert RxEnb* two cycles

before the end of the cell transfer, unless a back-to-back transfer is intended. The decoderesponse

timing between the RxEnb and the RxData is therefore two clock cycles.

Back-to-back reception of cells is possible when two or more cells have to be received

from the same port and the ATM layer device can receive the second cell. In this case of

back-to-back transfer the ATM layer device does not explicitly select the PHY port as

transfer to the same port is assumed. The second (or subsequent) cell is transferred

immediately after the previous one and the RxSOC is asserted to indicate the start of cell.

This is illustrated in Figure 4.11.