综合优化(synthesize)是指将HDL语言,原理图等设计输入翻译成由与或非门,RAM,触发器等基本逻辑单元组成的逻辑连接,也就是所谓的逻辑网表,并根据目标与要求(约束条件)优化所生成的逻辑连接,输出edf和edn等文件。
综合过程包括两个内容,一是对硬件语言源代码输入进行编译与逻辑层次上的优化,二是对编译结果进行逻辑映射与结构层次上的优化,最后生成逻辑网表。
综合结果的优劣直接影响布局布线结果的最终效能。综合结果的优劣是以使设计芯片的物理面积最小和工作频率最高为指标。当两者发生冲突时,一般采用速度优先的原则。
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****该程序实现了8位的奇偶校验***********************************************
*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity parity_check is
generic(size : integer :=8);
port(data_in:in std_logic_vector(size - 1 downto 0);
even_odd:in std_logic;
pa_out:out std_logic_vector(size downto 0));
end parity_check;
architecture Behavioral of parity_check is
signal temp:std_logic;
begin
process(even_odd,data_in)
begin
if(even_odd='1') then
temp<=data_in(7) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(3)xor data_in(2) xor data_in(1) xor data_in(0);
else
temp<=data_in(7) xor data_in(6) xor data_in(5) xor data_in(4) xor data_in(3)xor data_in(2) xor data_in(1) xor data_in(0) xor '1';
end if;
end process;
pa_out<=temp&data_in;
end Behavioral;
*******************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
ARCHITECTURE behavior OF test_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT parity_check
generic(size : integer := 8);
PORT(
data_in : IN std_logic_vector(size-1 downto 0);
even_odd : IN std_logic;
pa_out : OUT std_logic_vector(size downto 0)
);
END COMPONENT;
--Inputs
SIGNAL even_odd : std_logic := '0';
SIGNAL data_in : std_logic_vector(7 downto 0) := (others=>'0');
--Outputs
SIGNAL pa_out : std_logic_vector(8 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: parity_check PORT MAP(
data_in => data_in,
even_odd => even_odd,
pa_out => pa_out
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
data_in(7 downto 0)<="10001111";
even_odd<='1';
wait for 100 ns;
data_in(7 downto 0)<="11110000";
even_odd<='0';
wait for 100 ns;
data_in(7 downto 0)<="10001111";
even_odd<='0';
wait for 100 ns;
data_in(7 downto 0)<="11110000";
even_odd<='1';
wait; -- will wait forever
END PROCESS
END;
*******************************************************************************
使用verilog 语言编写的奇偶校验
`define DELAY 1
module parity_check(data_in,pa_in,even_odd,pa_out,error);
input[7:0];
input pa_in;
input even_odd;
output pa_out;
output error;
wire [7:0] data_in;
wire pa_in;
wire even_odd;
wire pa_out;
wire error;
assign #`DELAY pa_out=even_odd ? ^data_in[7:0]:~^data_in[7:0];
assign #`DELAY error=even_odd ? ^(data_in[7:0],pa_in):~^(data_in[7:0],pa_in);
endmodule;
*******************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity parity_check1 is
generic(size : integer :=8);
port(data_in:in std_logic_vector(size-1 downto 0);
pa_in:in std_logic;
even_odd:in std_logic;
error:out std_logic;
pa_out:out std_logic);
end parity_check1;
architecture Behavioral of parity_check1 is
begin
process(data_in,pa_in,even_odd)
begin
if(even_odd='0') then
pa_out<= not (data_in(size-1) xor data_in(size -2) xor data_in(size-3) xor data_in(size-4) xor data_in(size-5) xor data_in(size-6) xor data_in(size-7) xor data_in(size-8));
error<=not (pa_in xor data_in(size-1) xor data_in(size -2) xor data_in(size-3) xor data_in(size-4) xor data_in(size-5) xor data_in(size-6) xor data_in(size-7) xor data_in(size-8));
else
<