HDLBits Exams/review2015 fancytimer

题目描述：

This is the fifth component in a series of five exercises that builds a complex counter out of several smaller circuits. You may wish to do the four previous exercises first (counter, sequence recognizer FSM, FSM delay, and combined FSM).

We want to create a timer with one input that:

1. is started when a particular input pattern (1101) is detected,
2. shifts in 4 more bits to determine the duration to delay,
3. waits for the counters to finish counting, and
4. notifies the user and waits for the user to acknowledge the timer.

The serial data is available on the data input pin. When the pattern 1101 is received, the circuit must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration of the timer delay. I'll refer to this as the delay[3:0].

After that, the state machine asserts its counting output to indicate it is counting. The state machine must count for exactly (delay[3:0] + 1) * 1000 clock cycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count 6000 cycles. Also output the current remaining time. This should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for 1000 cycles. When the circuit isn't counting, the count[3:0] output is don't-care (whatever value is convenient for you to implement).

At that point, the circuit must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).

The circuit should reset into a state where it begins searching for the input sequence 1101.

Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once the 1101 and delay[3:0] have been read, the circuit no longer looks at the data input until it resumes searching after everything else is done. In this example, the circuit counts for 2000 clock cycles because the delay[3:0] value was 4'b0001. The last few cycles starts another count with delay[3:0] = 4'b1110, which will count for 15000 cycles.

翻译：

1.当检测到输入data为1101时启动，

2.通过接下来的4个时钟周期的data确定延迟时间，

3.等待计数器计数完成，

4.通知用户并等待答复。

延时时间由1101之后四个bit位（delay[3:0]）确定，延迟时间为(delay+1)*1000，count输出当前的延迟，计数期间counting位置1，延迟结束后通过断言输出done通知用户，并等待输入ack以开始下一次循环。有限状态机的初始状态为A。

 题目分析：

没啥好分析的，不废话，直接看状态机：

前四个状态检测1101，A状态通过四个周期读取延时时间，读完后进入B状态更新延迟时间delay并记一次数进入C状态，C状态通过计数（delay+1）*1000次后进入D状态并断言done等待用户确认，用户确认后返回A状态。

代码如下：

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    
    parameter A=4'b0000,B=4'b0001,C=4'b0010,D=4'b0011,E=4'b0100,F=4'b0101,G=4'b0110,H=4'b0111;
    reg [3:0] state,next;
    reg [11:0] counter;
    reg [3:0] delay;
    
    always@(*)
        begin
            case(state)
                A:next = data ? B : A;
                B:next = data ? C : A;
                C:next = data ? C : D;
                D:next = data ? E : A;
                E:next = (counter == 12'd0) ? F : E;
                F:next = G;
                G:next = (counter == 12'd0 && delay == 4'b0) ? H : G;
                H:next = ack ? A : H;
                default:next = A;
            endcase
        end
    
    always@(posedge clk)
        begin
            if(reset)
                begin
                    state = A;
                    counter = 12'd0;
                    delay = 4'b0;
                end
            else
                begin
                    if(state == D)
                        begin
                            counter = 12'd3;
                        end
                    else if(state == E)
                        begin
                        	counter--;
                            delay = {delay[2:0],data};
                        end
                    else if(state == F)
                        begin
                            counter = 12'd999 - 12'd1;
                        end
                    else if(state == G)
                        begin
                            if(counter == 12'd0)
                                begin
                                	counter = 12'd999;
                                    delay--;
                                end
                            else
                            	counter--;
                        end
                    state = next;
                end
        end

    assign count = delay;
    assign counting = (state == F | state == G);
    assign done = (state == H);
    
endmodule

 输出成功：