VCS和Verdi联合仿真Makefile脚本示例

#************parameter input*************
#※prepare the source list file and then make add the soucefile name
#for example ,the Verilog source file's name is vlog_list.f then :make norsim src_list=file_list
src_list = filelist
simv_name = simv
vpdpluse_name = vcdpluse
cov_file_name = coverage
vdb_name = $(simv_name)
#************constant command************
#compile
NOR_VCS = vcs -full64 -sverilog +v2k -timescale=1ns/1ns \
-debug_all \
+notimingcheck \
+nospecify \
+vcs+flush+all \
-o $(simv_name) \
-l compile.log \
-f $(src_list).f
#coverage compile switch
COV_SW = -cm line+cond+fsm+branch+tgl
#verdi dump wave compile option
VERDI_SW = -P /tools/synopsys/verdi/Verdi3_L-2016.06-1/share/PLI/VCS/linux64/novas.tab \
/tools/synopsys/verdi/Verdi3_L-2016.06-1/share/PLI/VCS/linux64/pli.a
#run option
RUN_GUI = -R -gui -l run.log
RUN_VPD = -R +vpdfile+$(vpdpluse_name).vpd -l run.log
RUN_COV = -R $(COV_SW) -cm_name $(vdb_name) -cm_dir ./$(cov_file_name) -l run.log
RUN_VER = -R +fsdb+autoflush -l run.log
#************command************
#normally sim
norsim:
	$(NOR_VCS) $(RUN_GUI)
#post-process
postsim:
	$(NOR_VCS) $(RUN_VPD)
	dve -vpd $(vpdpluse_name).vpd
#coverage
covsim:
	$(NOR_VCS) $(COV_SW) $(RUN_COV)
	dve -covdir $(cov_file_name).vdb
#verdi
#versim:
run_vcs:
	$(NOR_VCS) $(VERDI_SW) $(RUN_VER)
vd:
	verdi -sv -f $(src_list).f -ssf *.fsdb -nologo
#rm
clr:
	rm -rf *csrc ./*.daidir $(simv_name) *simv* DVE* ucli* *.vpd *.vdb *.log *.fsdb *novas* *.dat *Log *rc *conf

先使用

make run_vcs

进行VCS仿真

然后使用

make vd

用verid打开fsdb。

注意，在顶层testbench中要加入：

//dump fsdb
initial begin
    $fsdbDumpfile("top.fsdb");
    $fsdbDumpvars(0);
end

dump fsdb才行！！！