【I2C】THE I2C-BUS SPECIFICATION

1、Generation of clock signals on the I2C-bus is always the responsibility of master devices; each master generates its own clock signals when transfering data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow-slave device holding-down the clock line, or by another master when arbitration occurs.

2、When the bus is free, both lines are HIGH. 

3、Data on the I2C-bus can be transfered at rates of up to 100kbit/s in the Standard-mode, up to 400kbits/s in the Fast-mode, or up to 3.4Mbit/s in the High-speed mode.

4、The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.

5、A HIGH to low transition on the SDA line while SCL is HIGH is one such unique case. The situation indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

6、Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit(MSB) first.

7、Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse.

The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. Of course, set-up and hold times must be take into account.

8、All masters generate their own clock on the SCL line to transfer messages on the I2c-bus. Data is only valid during the HIGH period of the clock. A dfined clock is therefore needed for the bit-by-bit arbitration procedure to take place.

Clock sychronization is performed using the wired-AND connection of I2C-bus interfaces to the SCL line. This means thar a HIGH to LOW transition on the SCL line will cause the devices concered to start counting their LOW period and, once a device clock has gone LOW, it will hold the SCL line in that state until the clock HIGH state is reached. However, the LOW to HIGH transition of this clock may not change the state of the SCL line if another clock is still within its LOW period. The SCL line will therefore be held LOW by the device with the longest LOW period. Devices with shorter LOW periods enter a HIGH wait-state during this time.

When all devices concered have counted off their LOW period, the clock line will be released and go HIGH. There will then be no difference between the device clocks and  the state of the SCL line, and all the devices will start counting their HIGH periods. The first device to complete its HIGH period will again pull the SCL line LOW.

In this way, a synchronized SCL line is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by one with the shortest clock HIGH period.

 

转载于:https://www.cnblogs.com/bootblack/p/11461285.html