verilog hdl 时序逻辑电路0

testshixu.v

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    11:48:22 05/06/2017 
// Design Name: 
// Module Name:    testshixu 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module testshixu(iClk,oLed,rst);




//endmodule




//module led_run(iClk,oLed,rst);


input iClk;
input rst;
output [3:0] oLed;
reg [3:0] oLed;
reg [1:0] count;
reg [1:0] state;
wire clk;


always @(posedge iClk or negedge rst)
begin
  if(!rst)
     count = 0; 
      else
         count = count+1;
end


//assign clk=count[1];


 


always @(posedge iClk or negedge rst)
begin
    if(!rst)
       oLed <=4'b0000;
    else
       begin
         case(count)
           2'b00: oLed<=4'b0001;
           2'b01: oLed<=4'b0010;
           2'b10: oLed<=4'b0100;
           2'b11: oLed<=4'b1000;
         endcase
         //state=state+1;
       end
end
endmodule



test_testshixu.v

`timescale 1ns / 1ps



// Company: 
// Engineer:
//
// Create Date:   12:00:03 05/06/2017
// Design Name:   testshixu
// Module Name:   D:/ise147/prj/testshixu/test.v
// Project Name:  testshixu
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: testshixu
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 



module test;


// Inputs
reg iClk;
reg rst;


// Outputs
wire [3:0] oLed;
//reg [1:0] state;


// Instantiate the Unit Under Test (UUT)
testshixu uut (
.iClk(iClk), 
.oLed(oLed), 
.rst(rst)
);



    initial
    begin
      iClk = 1'b0;
      rst  = 1'b0;

      #5
      iClk = 1'b1;
      rst  = 1'b1;
    end
    always #10 
iClk = ~iClk;




      
endmodule