In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).
Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter IDLE = 3'b000,
START = 3'b001,
TRANS = 3'b011,
END = 3'b010,
ERR = 3'b110;
reg [2:0] state, next_state;
reg [3:0] cnt_data;
always@ (posedge clk)
if(reset)
cnt_data <= 4'b0;
else if(next_state == START)
cnt_data <= 4'b0;
else if(next_state == TRANS)
cnt_data <= cnt_data + 1'd1;
else
cnt_data <= cnt_data;
always@ (posedge clk)
if(reset)
state <= IDLE;
else
state <= next_state;
always@ (posedge clk)
if(reset)
done <= 0;
else if(next_state == END)
done <= 1;
else
done <= 0;
always@ (*)
case (state)
IDLE:
if(~in)
next_state <= START;
else
next_state <= IDLE;
START:
next_state <= TRANS;
TRANS:
if(cnt_data == 4'd8) begin
if(in)
next_state <= END;
else
next_state <= ERR;
end
else
next_state <= TRANS;
END:
if(in)
next_state <= IDLE;
else
next_state <= START;
ERR:
if(in)
next_state <= IDLE;
else
next_state <= ERR;
default:
next_state <= IDLE;
endcase
endmodule