verilog中的parameter和localparam的区别

parameter : 全局参数定义，可在整个设计中传递参数
localparam :仅限于当前模块的参数定义，跨模块不可用。

顶层例化:

  mem #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(6))
   u1 (
    .clka (adc_clk),
    .wea (adc_wr),
    .addra (adc_waddr),
    .dina (adc_wdata),
    .clkb (dma_clk),
    .addrb (dma_raddr),
    .doutb (dma_rdata_s));

或本模块例化

`timescale 1ns/100ps
module mem 
          #(parameter DATA_WIDTH = 16
            parameter ADDR_WIDTH =  5)
           (  
            input    clka,
            input    wea,
            input   [AW:0]  addra,
            input   [DW:0]  dina,
            input           clkb,
            input   [AW:0]  addrb,
            output  [DW:0]  doutb
           ); 

  localparam      DW = DATA_WIDTH - 1;
  localparam      AW = ADDR_WIDTH - 1;

  reg     [DW:0]  m_ram[0:((2**ADDR_WIDTH)-1)];
  reg     [DW:0]  doutb;

  always @(posedge clka) begin
    if (wea == 1'b1) begin
      m_ram[addra] <= dina;
    end
  end

  always @(posedge clkb) begin
    doutb <= m_ram[addrb];
  end

endmodule

原文地址：https://blog.csdn.net/yang2011079080010/article/details/51507904