PPC的MCU初始化

MMU初始化重要的有2个，TLB和LAW
    通过TLB，把EA(Effective address)转换为RA(Real Address)
    通过LAW，把RA送到物理总线上去，即总线地址
下面以MPC8560来举例

-------------------------- 格机格机格机格机格机格机 ------------------------------

Effective Address   -->    Virtual Address   -->   Real Address    --> Bus Addess
   EA 有效地址                VA 虚拟地址             RA 物理地址          总线地址
     32 bit                    41 bit                  32 bit         取决于地址总线位宽

下面是一张图，讲述了TLB把EA转换为RA的过程


第一步：根据 EA有效地址产生 VA虚拟地址。虚拟地址为 41位，构成如下：

bit[0], AS，地址空间域
    0 是和中断处理及系统级的代码和数据关联
    1 是应用程序的代码和数据 

    用户模式的程序运行时，一般 MSR[IS,DS]为 1，只允许访问应用程序的代码及数据地址空间。
    进入中断时，MSR[IS,DS]自带清 0，因此可以利用系统级的 TLB(TS=0)来访问中断处理相关的代码。 

bit[1-8]，TID，进程标识符
    由 PID寄存器提供，多数操作系统都未实现，默认 0

bit[9-40] 即原来的 EA地址 (页表号+页内offset，)


第二步：根据虚拟地址匹配TLB，匹配过程如下：

V域为 1，当前 TLB项有效；
MSR[IS,DS]和 TLB表项的 TS域一致；
TID一致或者 TLB表达 TID为 0，全局共享；
由表项的SIZE域根据公式 n = 32–log2 (page size in bytes)计算虚拟地址中 EPN的值，然后和TLB的 EPN域进行匹配且匹配成功。

第三步，根据TLB生成 RA

TLB匹配成功后，将提取 TLB表的 RPN和 ERPN域，构成 RA物理实际地址的页编号部分，而页内偏移由 EA的低地址部分提供，相关构成如下：

RA = ERPN0:3 || RPN0:n–1 || EAn:31


第四步，匹配LAW，生成总线地址

用RA来检索LAW entry，下面是一个LAW的例子
 
比如命中了 PCI law entry，就会通过PCI的相关地址转换寄存器生成bus address总线地址，
然后送到PCI总线上

-------------------------- 格机格机格机格机格机格机 ------------------------------

基本原理是用一些静态数组的值来初始化 TLB 和 LAW 的 entry

1. ######################## 文件 /uboot/cpu/mpc8560/start.S #################
   
2. 221 /*
   
3. 222 * Invalidate MMU L1/L2
   
4. 223 *
   
5. 224 * Note: There is a fixup earlier for Errata CPU4 on
   
6. 225 * Rev 1 parts that must precede this MMU invalidation.
   
7. 226 */
   
8. 227 li r2, 0x001e
   
9. 228 mtspr MMUCSR0, r2
   
10. 229 isync
    
11. 230
    
12. 231 /*
    
13. 232 * Invalidate all TLB0 entries. 禁用所有TLB0的entry ， 只有4个？
    
14. 233 */
    
15. 234 li r3,4
    
16. 235 li r4,0
    
17. 236 tlbivax r4,r3
    
18. 237 /*
    
19. 238 * To avoid REV1 Errata CPU6 issues, make sure
    
20. 239 * the instruction following tlbivax is not a store.
    
21. 240 */
    
22. 241
    
23. 242 /*
    
24. 243 * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
    
25. 244 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
    
26. 245 * region before we can access any CCSR registers such as L2
    
27. 246 * registers, Local Access Registers,etc. We will also re-allocate
    
28. 247 * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
    
29. 248 *
    
30. 249 * Please refer to board-specif directory for TLB1 entry configuration.
    
31. 250 * (e.g. board/<yourboard>/init.S)
    
32. 251 *
    
33. 252 */
    
34. 253 bl tlb1_entry  /* 注意，tlb1_entry 这个section可以看做一个数组，来描述TLB0和TLB1 */
    
35. 254 mr r5,r0       /* 注意，r0 里存的是第68行的 EA， 此EA里保存的是TLB entry数组的大小值 */
    
36. 255 li r1,0x0020   /* max 16 TLB1 plus some TLB0 entries, 我日，这改Counter寄存器有毛用？*/
    
37. 256 mtctr r1
    
38. 257 lwzu r4,0(r5) /* how many TLB1 entries we actually use 从(r5中存的)EA中load值到r4中，现在r4里面存的是TLB entry 的个数*/ 
    
39. 258
    
40. 259 0: cmpwi r4,0  /* 这就是循环初始化TLB entry了，每初始化一个，r4就减1，r4为0时跳转到第276行*/
    
41. 260 beq 1f
    
42. 261 lwzu r0,4(r5)   /* r5 在不断的增加4，即EA在不断的增加4，即在遍历TLB entry 数组 */
    
43. 262 lwzu r1,4(r5)
    
44. 263 lwzu r2,4(r5)
    
45. 264 lwzu r3,4(r5)
    
46. 265 mtspr MAS0,r0   /* 用从TLB entry 数组来初始化 TLB */
    
47. 266 mtspr MAS1,r1
    
48. 267 mtspr MAS2,r2
    
49. 268 mtspr MAS3,r3
    
50. 269 isync
    
51. 270 msync
    
52. 271 tlbwe
    
53. 272 isync
    
54. 273 addi r4,r4,-1
    
55. 274 bdnz 0b
    
56. 275
    
57. 276 1:
    
58. 277 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
    
59. 278 /* Special sequence needed to update CCSRBAR itself 即CCSR重定向*/
    
60. 279 lis r4, CFG_CCSRBAR_DEFAULT@h
    
61. 280 ori r4, r4, CFG_CCSRBAR_DEFAULT@l
    
62. 281
    
63. 282 lis r5, CFG_CCSRBAR@h
    
64. 283 ori r5, r5, CFG_CCSRBAR@l
    
65. 284 srwi r6,r5,12
    
66. 285 stw r6, 0(r4)
    
67. 286 isync
    
68. 287
    
69. 288 lis r5, 0xffff
    
70. 289 ori r5,r5,0xf000
    
71. 290 lwz r5, 0(r5)
    
72. 291 isync
    
73. 292
    
74. 293 lis r3, CFG_CCSRBAR@h
    
75. 294 lwz r5, CFG_CCSRBAR@l(r3)
    
76. 295 isync
    
77. 296 #endif
    
78. 297
    
79. 298
    
80. 299 /* set up local access windows, defined at board/<boardname>/init.S */
    
81. 300 lis r7,CFG_CCSRBAR@h
    
82. 301 ori r7,r7,CFG_CCSRBAR@l
    
83. 302
    
84. 303 bl law_entry      /* 注意，law_entry 这个section可以看做一个数组，来描述LAW */
    
85. 304 mr r6,r0          /* 注意，r0 里存的是第321行的 EA， 此EA里保存的是LAW entry数组的大小值 */
    
86. 305
    
87. 306 li r1,0x0009      /* 10 LAWs for MPC8548. The LAWs value in board/init.S must not over the CPU max LAWs. 又是Counter寄存器，初始化它干什么用的？*/
    
88. 307 mtctr r1
    
89. 308 lwzu r5,0(r6) /* how many windows we actually use 从(r6中存的)EA中load值到r5中，现在r5里面存的是TLB entry 的个数*/
    
90. 309
    
91. 310 li r2,0x0c28     /* the first pair is reserved for boot-over-rio-or-pci */
    
92. 311 li r1,0x0c30
    
93. 312
    
94. 313 0: cmpwi r5,0    /* 循环初始化LAW entry，每初始化一个，r5减1，r5为0时跳转到第325行 */
    
95. 314 beq 1f
    
96. 315 lwzu r4,4(r6)    /* 从(r6中存的)EA中load值, r6也跟着不断增加，即遍历LAW数组 r6 <-- r6+4 r4 <-- *(r6) */
    
97. 316 lwzu r3,4(r6)
    
98. 317 stwx r4,r7,r2    /* 写LAWBAR寄存器 *(r7+r2) <-- r4 */
    
99. 318 stwx r3,r7,r1
    
100. 319 addi r5,r5,-1
     
101. 320 addi r2,r2,0x0020    /* LAWBAR[0-7]寄存器的偏移量是0x0020 r2 <-- r2 + 0x0020 */
     
102. 321 addi r1,r1,0x0020
     
103. 322 bdnz 0b
     
104. 323
     
105. 324 /* Jump out the last 4K page and continue to 'normal' start */
     
106. 325 1: bl 3f
     
107. 326 b _start
     
108. 327
     
109. 328 3: li r0,0
     
110. 329 mtspr SRR1,r0 /* Keep things disabled for now */
     
111. 330 mflr r1
     
112. 331 mtspr SRR0,r1
     
113. 332 rfi
     
114. 
     
115. 
     
116. ############### 文件 board/pq37pc/pq37pc_8560/init.S ########################
     
117. 
     
118.  33 /*
     
119.  34 * TLB0 and TLB1 Entries
     
120.  35 *
     
121.  36 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
     
122.  37 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
     
123.  38 * these TLB entries are established.
     
124.  39 *
     
125.  40 * The TLB entries for DDR are dynamically setup in spd_sdram()
     
126.  41 * and use TLB1 Entries 8 through 15 as needed according to the
     
127.  42 * size of DDR memory.
     
128.  43 *
     
129.  44 * MAS0: tlbsel, esel, nv
     
130.  45 * MAS1: valid, iprot, tid, ts, tsize
     
131.  46 * MAS2: epn, sharen, x0, x1, w, i, m, g, e
     
132.  47 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
     
133.  48 */
     
134.  49
     
135.  50 #define entry_start \
     
136.  51 mflr r1 ; \     //把LR的值，即bl tlb1_entry 的下一条指令的EA 保存到 r1 中(即第254行的地址)
     
137.  52 bl 0f ;         // 就是直接跳到0处执行代码，起始就是符号entry_end处(即第55行)
     
138.  53
     
139.  54 #define entry_end \
     
140.  55 0: mflr r0 ; \ //把LR的值，即bl 0f的下一条指令的EA 存到 r0 中 (即第68行)
     
141.  56 mtlr r1 ; \    // 把r1的值放到LR中，LR中值是 bl tlb1_entry的下一条指令的EA (即第254行的地址)
     
142.  57 blr ;          // 跳转到LR处，即执行 bl tlb1_entry的下一条指令 (即第254行的地址)
     
143.  58
     
144.  59
     
145.  60 .section .bootpg, "ax"
     
146.  61 .globl tlb1_entry
     
147.  62 tlb1_entry:
     
148.  63 entry_start
     
149.  64
     
150.  65 /*
     
151.  66 * Number of TLB0 and TLB1 entries in the following table
     
152.  67 */
     
153.  68 .long 21
     
154.  69
     
155.  70 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
     
156.  71 /*
     
157.  72 * TLB0 4K Non-cacheable, guarded
     
158.  73 * 0xff700000 4K Initial CCSRBAR mapping
     
159.  74 *
     
160.  75 * This ends up at a TLB0 Index==0 entry, and must not collide
     
161.  76 * with other TLB0 Entries.
     
162.  77 */
     
163.  78 .long TLB1_MAS0(0, 0, 0)
     
164.  79 .long TLB1_MAS1(1, 0, 0, 0, 0)
     
165.  80 .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
     
166.  81 .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
     
167.  82 #else
     
168.  83 #error("Update the number of table entries in tlb1_entry")
     
169.  84 #endif
     
170.  85
     
171.  86 /*
     
172.  87 * TLB0 16K Cacheable, non-guarded
     
173.  88 * 0xd001_0000 16K Temporary Global data for initialization
     
174.  89 *
     
175.  90 * Use four 4K TLB0 entries. These entries must be cacheable
     
176.  91 * as they provide the bootstrap memory before the memory
     
177.  92 * controler and real memory have been configured.
     
178.  93 *
     
179.  94 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
     
180.  95 * and must not collide with other TLB0 entries.
     
181.  96 */
     
182.  97 .long TLB1_MAS0(0, 0, 0)
     
183.  98 .long TLB1_MAS1(1, 0, 0, 0, 0)
     
184.  99 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),0,0,0,0,0,0,0,0)
     
185. 100 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),0,0,0,0,0,1,0,1,0,1)
     
186. 101
     
187. 102 .long TLB1_MAS0(0, 0, 0)
     
188. 103 .long TLB1_MAS1(1, 0, 0, 0, 0)
     
189. 104 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),0,0,0,0,0,0,0,0)
     
190. 105 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),0,0,0,0,0,1,0,1,0,1)
     
191. 106
     
192. 107 .long TLB1_MAS0(0, 0, 0)
     
193. 108 .long TLB1_MAS1(1, 0, 0, 0, 0)
     
194. 109 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),0,0,0,0,0,0,0,0)
     
195. 110 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),0,0,0,0,0,1,0,1,0,1)
     
196. 111
     
197. 112 .long TLB1_MAS0(0, 0, 0)
     
198. 113 .long TLB1_MAS1(1, 0, 0, 0, 0)
     
199. 114 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),0,0,0,0,0,0,0,0)
     
200. 115 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),0,0,0,0,0,1,0,1,0,1)
     
201. 116
     
202. 117
     
203. 118 /*
     
204. 119 * TLB 0: 16M Non-cacheable, guarded
     
205. 120 * 0xfff80000 512k FLASH
     
206. 121 * Out of reset this entry is only 4K.
     
207. 122 */
     
208. 123 .long TLB1_MAS0(1, 0, 0)
     
209. 124 .long TLB1_MAS1(1, 1, 0, 0, CFG_MAX_FLASH_TSIZE)
     
210. 125 .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_FLASH_BASE), 0,0,0,0,1,0,1,0)
     
211. 126 .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_FLASH_BASE), 1,1,1,1,1,1,1,1,0,1)
     
212. 127
     
213. 128
     
214. 129
     
215. 130 /*
     
216. 131 * TLB 1: 256M Non-cacheable, guarded
     
217. 132 * 0x80000000 256M PCI1 MEM First half
     
218. 133 */
     
219. 134 .long TLB1_MAS0(1, 9, 0)
     
220. 135 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
221. 136 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
     
222. 137 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
     
223. 138
     
224. 139 /*
     
225. 140 * TLB 2: 256M Non-cacheable, guarded
     
226. 141 * 0x90000000 256M PCI1 MEM Second half
     
227. 142 */
     
228. 143 .long TLB1_MAS0(1, 6, 0)
     
229. 144 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
230. 145 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),0,0,0,0,1,0,1,0)
     
231. 146 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),0,0,0,0,0,1,0,1,0,1)
     
232. 147
     
233. 148
     
234. 149 #if 0
     
235. 150 /*
     
236. 151 * TLB 3: 256M Non-cacheable, guarded
     
237. 152 * 0xa0000000 256M Rapid IO MEM First half
     
238. 153 */
     
239. 154 .long TLB1_MAS0(1, 7, 0)
     
240. 155 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
241. 156 .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
     
242. 157 .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
     
243. 158
     
244. 159 /*
     
245. 160 * TLB 4: 256M Non-cacheable, guarded
     
246. 161 * 0xb0000000 256M Rapid IO MEM Second half
     
247. 162 */
     
248. 163 .long TLB1_MAS0(1, 8, 0)
     
249. 164 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
250. 165 .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),0,0,0,0,1,0,1,0)
     
251. 166 .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),0,0,0,0,0,1,0,1,0,1)
     
252. 167
     
253. 168 #endif
     
254. 169
     
255. 170 /*
     
256. 171 * in my design, Rapid IO not use, just use it's marco for other interface
     
257. 172 * TLB 3:
     
258. 173 * 0xa0000000 256M Rapid IO MEM Second half
     
259. 174 */
     
260. 175 .long TLB1_MAS0(1, 15, 0)
     
261. 176 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
262. 177 .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE ),0,0,0,0,1,0,1,0)
     
263. 178 .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE ),0,0,0,0,0,1,0,1,0,1)
     
264. 179
     
265. 180 /*
     
266. 181 * TLB 4: 64M Non-cacheable, guarded
     
267. 182 * 0xe000_0000 1M CCSRBAR
     
268. 183 * 0xe200_0000 16M PCI1 IO
     
269. 184 */
     
270. 185 .long TLB1_MAS0(1, 1, 0)
     
271. 186 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
     
272. 187 .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
     
273. 188 .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
     
274. 189
     
275. 190 /*
     
276. 191 * TLB 5: 16K Non-cacheable, guarded
     
277. 192 * 0xf8000000 16K registers
     
278. 193 */
     
279. 194 .long TLB1_MAS0(1, 10, 0)
     
280. 195 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) /*BOOKE_PAGESZ_16K for LED_BASE*/
     
281. 196 .long TLB1_MAS2(E500_TLB_EPN(CFG_LED_BASE), 0,0,0,0,1,0,1,0)
     
282. 197 .long TLB1_MAS3(E500_TLB_RPN(CFG_LED_BASE), 0,0,0,0,0,1,0,1,0,1)
     
283. 198
     
284. 199
     
285. 200 /*
     
286. 201 * TLB 6,7: 128M Non-cacheable, guarded
     
287. 202 * 0xf0000000 128M registers
     
288. 203 */
     
289. 204 .long TLB1_MAS0(1, 11, 0)
     
290. 205 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
     
291. 206 .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
     
292. 207 .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
     
293. 208
     
294. 209 .long TLB1_MAS0(1, 12, 0)
     
295. 210 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
     
296. 211 .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x04000000), 0,0,0,0,1,0,1,0)
     
297. 212 .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x04000000), 0,0,0,0,0,1,0,1,0,1)
     
298. 213
     
299. 214
     
300. 215
     
301. 216 /*
     
302. 217 * TLB 8,9,10,11: for 1G DDR
     
303. 218 * TLB 8 0x00000000 256M DDR System memory
     
304. 219 * TLB 9 0x10000000 256M DDR System memory
     
305. 220 * TLB 10 0x20000000 256M DDR System memory
     
306. 221 * TLB 11 0x30000000 256M DDR System memory
     
307. 222 * Without SPD EEPROM configured DDR, this must be setup manually.
     
308. 223 * Make sure the TLB count at the top of this table is correct.
     
309. 224 * Likely it needs to be increased by two for these entries.
     
310. 225 */
     
311. 226 .long TLB1_MAS0(1, 2, 0)
     
312. 227 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
313. 228 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
     
314. 229 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
     
315. 230
     
316. 231 .long TLB1_MAS0(1, 3, 0)
     
317. 232 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
318. 233 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x10000000),0,0,0,0,0,0,0,0)
     
319. 234 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x10000000),0,0,0,0,0,1,0,1,0,1)
     
320. 235
     
321. 236 .long TLB1_MAS0(1, 4, 0)
     
322. 237 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
323. 238 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x20000000),0,0,0,0,0,0,0,0)
     
324. 239 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x20000000),0,0,0,0,0,1,0,1,0,1)
     
325. 240
     
326. 241 .long TLB1_MAS0(1, 5, 0)
     
327. 242 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
328. 243 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x30000000),0,0,0,0,0,0,0,0)
     
329. 244 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x30000000),0,0,0,0,0,1,0,1,0,1)
     
330. 245
     
331. 246 //follow is added by zhangsy
     
332. 247 /*
     
333. 248 * TLB 12,13,14,15: for 1G DDR
     
334. 249 * TLB 12 0x40000000 256M DDR System memory
     
335. 250 * TLB 13 0x50000000 256M DDR System memory
     
336. 251 * TLB 14 0x60000000 256M DDR System memory
     
337. 252 * TLB 15 0x70000000 256M DDR System memory
     
338. 253 */
     
339. 254
     
340. 255 .long TLB1_MAS0(1, 7, 0)
     
341. 256 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
342. 257 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x40000000), 0,0,0,0,0,0,0,0)
     
343. 258 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x40000000), 0,0,0,0,0,1,0,1,0,1)
     
344. 259
     
345. 260 .long TLB1_MAS0(1, 8, 0)
     
346. 261 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
347. 262 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x50000000),0,0,0,0,0,0,0,0)
     
348. 263 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x50000000),0,0,0,0,0,1,0,1,0,1)
     
349. 264
     
350. 265 .long TLB1_MAS0(1, 13, 0)
     
351. 266 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
352. 267 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x60000000), 0,0,0,0,0,0,0,0)
     
353. 268 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x60000000), 0,0,0,0,0,1,0,1,0,1)
     
354. 269
     
355. 270 .long TLB1_MAS0(1, 14, 0)
     
356. 271 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
     
357. 272 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x70000000),0,0,0,0,0,0,0,0)
     
358. 273 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x70000000),0,0,0,0,0,1,0,1,0,1)
     
359. 274
     
360. 275
     
361. 276 entry_end
     
362. 277
     
363. 278 /*
     
364. 279 * LAW(Local Access Window) configuration:
     
365. 280 *
     
366. 281 * 0x0000_0000 0x7fff_ffff DDR 2G
     
367. 282 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
     
368. 283 * 0xc000_0000 0xdfff_ffff RapidIO 512M
     
369. 284 * 0xe000_0000 0xe000_ffff CCSR 1M
     
370. 285 * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
     
371. 286 * 0xf000_0000 0xf3ff_ffff SDRAM 64M
     
372. 287 * 0xf800_0000 0xf800_7fff DEBUG LED and board ID 16K
     
373. 288 * 0xff80_0000 0xffbf_ffff FLASH (2nd bank) 4M
     
374. 289 * 0xffc0_0000 0xffff_ffff FLASH (boot bank) 4M
     
375. 290 *
     
376. 291 * Notes:
     
377. 292 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
     
378. 293 * If flash is 8M at default position (last 8M), no LAW needed.
     
379. 294 */
     
380. 295
     
381. 296 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
     
382. 297 #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_2G))
     
383. 298
     
384. 299 /*
     
385. 300 * Rapid IO at 0xc000_0000 for 512 M
     
386. 301 */
     
387. 302 #define LAWBAR3 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
     
388. 303 #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
     
389. 304
     
390. 305
     
391. 306
     
392. 307 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
     
393. 308 #define LAWBAR4 ((CFG_LBC_BASE_1>>12) & 0xfffff)
     
394. 309 #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI | (LAWAR_SIZE & LAWAR_SIZE_512M))
     
395. 310
     
396. 311
     
397. 312
     
398. 313 #define LAWBAR5 ((CFG_LBC_BASE_3>>12) & 0xfffff)
     
399. 314 #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
     
400. 315
     
401. 316
     
402. 317 .section .bootpg, "ax"
     
403. 318 .globl law_entry
     
404. 319 law_entry:
     
405. 320 entry_start
     
406. 321 .long 0x04
     
407. 322 .long LAWBAR0,LAWAR0
     
408. 323 .long LAWBAR3,LAWAR3
     
409. 324 .long LAWBAR4,LAWAR4
     
410. 325 .long LAWBAR5,LAWAR5
     
411. 326 entry_end