something about PCIe

Went over my excerpts on PCIe protocol which I made before. Although I really dont have time for that, but had to - coz in the long run it should be beneficial for me. A few cents are listed below:

1. the latency of PCIe is only 120ns invariant with payload size!

The test condition should be port to port on one sw. This should be purely switching latency and not including initialization. Well, I dont know how the PCIe initialization is processed yet. I didn't find a figure describing this process in PCI_Express_Base_r3.0. Looks PCI SIG folks don't like to spend time drawing graphs very much - compared to SAS standard, the PCIe one looks so non-graphic and boring. Guess the fast prevailing status of SAS could partially due to its eyecatching colorful standard:). If RapidIO makes its standard much easier to read than PCIe, it should help it in replacing PCIe.

2. the frame format of PCIe is to encapsulate TLP into LLP.

The following things I am not sure yet:

Now that TLP has its own STP and LCRC, multiple TLPs should be able to mapped into one LLP. Dont know about the number range of the TLP a LLP can carry?

Likewise, LLP has its own SDP and CRC?

Addressing info is contained in TLP packet header?

DLLP is a special type of frame added in PCIe for flow control purpose?

 Will get clear on above in the future.

3. pinout of different links.

x1: 24+12

x4: 36+3x8+4=64

x8: 64+4x8+2=98

x16: 98+8x8+2=164