全加器门级（结构级），数据流，行为级实现

最新推荐文章于 2023-05-03 19:59:23 发布

geter_CS

最新推荐文章于 2023-05-03 19:59:23 发布

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分类专栏：设计文章标签： verilog 全加器

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本文详细介绍了1位全加器的门级结构实现，通过逻辑门操作实现加法，并与行为级实现进行比较，展示了从电路级到高级抽象的不同实现方式。随后，扩展到4位全加器，分别展示了门级、数据流和行为级的实现，便于理解不同层次的电路设计。

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1位全加器，门结构实现：

module top_module ();
    reg clk=0;
    always #5 clk = ~clk;  // Create clock with period=10
    initial `probe_start;   // Start the timing diagram

    `probe(clk);        // Probe signal "clk"

    // A testbench
    reg ain,bin,cin;
    initial begin
        ain=0;
        bin=0;
        cin=0;
        #5 ain=1;
           bin=1;
        #5 ain=0;
           bin=0;
        #5 ain=1;
           cin=1;
        #5 bin=1;
        #60 $finish;            // Quit the simulation
    end
    full_add add(.ain(ain),.bin(bin),.cin(cin));  // Sub-modules work too.
endmodule
module  full_add(input ain,bin,cin,output sum,count);
    wire m1,m2,m3;
    wire s1;
    and (m1,ain,bin),
        (m2,ain,cin),
        (m3,bin,cin);
    xor (sum,ain,bin,cin);
    or  (count,m1,m2,m3);
    `probe(sum);
    `probe(ain);
    `probe(bin);
    `probe(cin);
    `probe(count);
endmodule

结果：

1位全加器数据流实现：

module top_module ();
    reg clk=0;
    always #5 clk = ~clk;  // Create clock with period=10
    initial `probe_start;   // Start the timing diagram

    `probe(clk);        // Probe signal "clk"

    // A testbench
    reg ain,bin,cin;
    initial begin
        ain=0;
        bin=0;
        cin=0;
        #5 ain=1;
           bin=1;
        #5 ain=0;
           bin=0;
        #5 ain=1;
           cin=1;
        #5 bin=1;
        #60 $finish;            // Quit the simulation
    end
    full_add add(.ain(ain),.bin(bin),.cin(cin));  // Sub-modules work too.
endmodule
module  full_add(input ain,bin,cin,output sum,count);
    assign sum=ain^bin^cin;
    assign count=(ain&bin)|(ain&bin)|(bin&cin);
    `probe(sum);
    `probe(ain);
    `probe(bin);
    `probe(cin);
    `probe(count);
endmodule

1位全加器行为级实现：

module top_module ();
    reg clk=0;
    always #5 clk = ~clk;  // Create clock with period=10
    initial `probe_start;   // Start the timing diagram

    `probe(clk);        // Probe signal "clk"

    // A testbench
    reg ain,bin,cin;
    initial begin
        ain=0;
        bin=0;
        cin=0;
        #5 ain=1;
           bin=1;
        #5 ain=0;
           bin=0;
        #5 ain=1;
           cin=1;
        #5 bin=1;
        #60 $finish;            // Quit the simulation
    end
    full_add add(.ain(ain),.bin(bin),.cin(cin));  // Sub-modules work too.
endmodule
module  full_add(input ain,bin,cin,output sum,count);
    reg sum,count;
    always @(ain or bin or cin)begin
    sum=ain+cin+bin;//ain^bin^cin
    count=(ain&bin)|(ain&cin)|(bin&cin); 
    end
    `probe(sum);
    `probe(ain);
    `probe(bin);
    `probe(cin);
    `probe(count);
endmodule

结果：

4位全加器门级结构实现：

module top_module ();
    reg clk=0;
    always #5 clk = ~clk;  // Create clock with period=10
    initial `probe_start;   // Start the timing diagram

    `probe(clk);        // Probe signal "clk"

    // A testbench
    reg [3:0] ain,bin;
    reg cin;
    initial begin
        ain=0;
        bin=0;
        cin=0;
        #5 ain=2;
           bin=3;
        #5 ain=4;
           bin=2;
        #5 ain=14;
           cin=1;
        #5 bin=1;
        #60 $finish;            // Quit the simulation
    end
    four_add add(.ain(ain),.bin(bin),.cin(cin));  // Sub-modules work too.
endmodule
module  full_add(input ain,bin,cin,output sum,count);
    wire m1,m2,m3;
    wire s1;
    and (m1,ain,bin),
        (m2,ain,cin),
        (m3,bin,cin);
    xor (sum,ain,bin,cin);
    or  (count,m1,m2,m3);
endmodule
module four_add(ain,bin,cin,sum,count);
    input [3:0] ain,bin,cin;
    output count;
    output [3:0] sum;
    wire cin1,cin2,cin3;
    full_add add0(ain[0],bin[0],cin,sum[0],cin1);
    full_add add1(ain[1],bin[1],cin1,sum[1],cin2);
    full_add add2(ain[2],bin[2],cin2,sum[2],cin3);
    full_add add3(ain[3],bin[3],cin3,sum[3],count);
    `probe(sum);
    `probe(ain);
    `probe(bin);
    `probe(cin);
    `probe(count);
endmodule

结果：

4位全加器数据流级实现：

module top_module ();
    reg clk=0;
    always #5 clk = ~clk;  // Create clock with period=10
    initial `probe_start;   // Start the timing diagram

    `probe(clk);        // Probe signal "clk"

    // A testbench
    reg [3:0] ain,bin;
    reg cin;
    initial begin
        ain=0;
        bin=0;
        cin=0;
        #5 ain=2;
           bin=3;
        #5 ain=4;
           bin=2;
        #5 ain=14;
           cin=1;
        #5 bin=1;
        #60 $finish;            // Quit the simulation
    end
    four_add add(.ain(ain),.bin(bin),.cin(cin));  // Sub-modules work too.
endmodule

module four_add(ain,bin,cin,sum,count);
    input [3:0] ain,bin,cin;
    output count;
    output [3:0] sum;
    assign {count,sum}=ain+bin+cin;

    `probe(sum);
    `probe(ain);
    `probe(bin);
    `probe(cin);
    `probe(count);
endmodule

结果：

4位全加器行为级实现：

module top_module ();
    reg clk=0;
    always #5 clk = ~clk;  // Create clock with period=10
    initial `probe_start;   // Start the timing diagram

    `probe(clk);        // Probe signal "clk"

    // A testbench
    reg [3:0] ain,bin;
    reg cin;
    initial begin
        ain=0;
        bin=0;
        cin=0;
        #5 ain=2;
           bin=3;
        #5 ain=4;
           bin=2;
        #5 ain=14;
           cin=1;
        #5 bin=1;
        #60 $finish;            // Quit the simulation
    end
    four_add add(.ain(ain),.bin(bin),.cin(cin));  // Sub-modules work too.
endmodule

module four_add(ain,bin,cin,sum,count);
    input [3:0] ain,bin,cin;
    output reg count;
    output reg [3:0] sum;
   
    always @(*) begin
        {count,sum}=ain+bin+cin;
    end
    `probe(sum);
    `probe(ain);
    `probe(bin);
    `probe(cin);
    `probe(count);
endmodule