VCS视频学习中的一个例子代码：dff.v和dff_tb.v

前言

VCS课程中的一个例子！

dff.v

//r/dff_exp.v 
 

 
module dff_exp(
	//Inputs
    input wire clk_i,
    input wire rst_l_i,
    input wire d,
	//Outputs
    output reg q
    );
	//........................................................
	//reg define area
	//........................................................
    reg q1;
	
	//........................................................
    //第一种实现方式 
	//........................................................	
    `ifdef DFF_STYLE1  
    always @(posedge clk_i, negedge rst_l_i) begin
        if (!rst_l_i)
          q1 <= 1'b0;
        else
          q1 <= d;
    end
 
    always @(posedge clk_i, negedge rst_l_i) begin
        if(!rst_l_i)
          q <= 1'b0;
        else
          q <= q1;
    end
    `endif
	
	//........................................................
    //第二种实现方式
	//........................................................
   `ifdef DFF_STYLE2
    always @(posedge clk_i, negedge rst_l_i) begin
        if (!rst_l_i)
          q1 = 1'b0;
        else
          q1 = d;
    end
 
    always @(posedge clk_i, negedge rst_l_i) begin
        if(!rst_l_i)
          q = 1'b0;
        else
          q = q1;
    end
    `endif
	
	 //第三种实现方式  
    `ifdef DFF_STYLE3  
    always @(posedge clk_i, negedge rst_l_i) begin
        if (!rst_l_i) begin
          q1 <= 1'b0;
          q <= 1'b0;
        end else begin
          q1 <= d;
          q <= q1;
        end
    end
    `endif
 
    //第四种实现方式
   `ifdef DFF_STYLE4
    always @(posedge clk_i, negedge rst_l_i) begin
        if (!rst_l_i) begin
          q1 = 1'b0;
          q = 1'b0;
        end
        else begin
          q1 = d;
          q = q1;
        end
    end
    `endif
	
	 //第五种实现方式  
    `ifdef DFF_STYLE5 
    always @(posedge clk_i, negedge rst_l_i) begin
        if (!rst_l_i) begin
          q1 <= 1'b0;
          q <= 1'b0;
        end else begin
          q <= q1;
		  q1 <= d;
        end
    end
    `endif
 
    //第六种实现方式
	
   `ifdef DFF_STYLE6
    always @(posedge clk_i, negedge rst_l_i) begin
        if (!rst_l_i) begin
          q = 1'b0;
		  q1 = 1'b0; 
        end else begin
          q = q1;
		  q1 = d;
        end
    end
    `endif
	
	//第七种实现方式  
    `ifdef DFF_STYLE5 
    always @(posedge clk_i, negedge rst_l_i) begin
        if (!rst_l_i) begin
          {q,q1} <= 2'b0;
        end else begin
           {q,q1} <= {q1,d};
        end
    end
    `endif
 
    //第八种实现方式
	
   `ifdef DFF_STYLE6
    always @(posedge clk_i, negedge rst_l_i) begin
        if (!rst_l_i) begin
          {q,q1} = 2'b0; 
        end else begin
          {q,q1} = {q1,d};
        end
    end
    `endif
 
endmodule//dff_exp

dff_tb.v

`timescale 1ns/1ns

module dd_tb;

//..................................................
//reg &wire define
//..................................................
	wire clk_i;
	wire rst_l_i;
	wire d;
	reg q;
	
//..................................................
//clock & reset & d generate
//..................................................

	initial begin
		clk_i <=1'b0;
		forever #5 clk_i <= -clk_i;
	end
	
	initial begin
		rst_l_i <= 1'b1;
		repeat (2) @ (posedge clk_i);
		rst_l_i <= 1'b0;
		repeat (2) @ (posedge clk_i);
		rst_l_i <= 1'b1;
		repeat (20) @ (posedge clk_i);
		$finish(2);
	end
	
	initial begin
		forever begin
			@(posedge clk_i);
			d <= 1'b0;
			@(posedge cllk_i);
			d <= 1'b1;		
		end
	end
	
//..................................................
//Instance of dff_exp
//..................................................
	dff_exp u_dff_exp{
		//Inputs
		.clk_i       ( clk_i   ),
		.rst_l_i     ( rst_l_i ),
		.d           ( d       ),
		//Outputs
		.q           ( q       )
   	};
	
//..................................................
//dump file
//..................................................
	initial begin
		$vcdpluson();
	end
endmodule//dff_tb

Makefile

.PHONY:com sim cov clean

OUTPUT = simv_dff_exp
ALL_DEFINE = +define+DUMP_FSDB
ALL_DEFINE += +define+DFF_STYLE22
#code coverage command
CM = -cm line+cond+fsm+branch+tgl
CM_NAME = -cm_name $(OUTPUT)
CM_DIR = -cm_dir ./$(OUTPUT).vdb

# vpd file name
VPD_NAME = +vpdfiles+$(OUTPUT).vpd

#coompile command
vcs = vcs -sverilog +v2k -timescale=1ns/1ns              \
	-debug_all                                           \
	+nontimingcheck                                      \
	+nospecify                                           \
	+vcs+flush+all                                       \
	$(CM)                                                \
	$(CM_NAME)                                           \
	$(CM_DIR)                                            \
	$(ALL_DEFINE)                                        \
	$(VPD_NAME)                                          \
	-o $(OUTPUT)                                         \
	-l compile.log

#simulation command
SIM = ./$(OUTPUT)                \
			$(CM) $(CM_NAME) $(CM_DIR) \
			$(VPD_NAME)                \
			-l $(OUTPUT).log


# start compile
com:
	$(vcs) -f file_list.f

#start simulation
sim:
	$(SIM)

# show the coverage
cov:
	dve -covdir *.vdb &
debug:
	dve -vpd $(OUTPUT).vpd &


# start clean
clean:
	rm -rf ./csrc *.daidir ./csrc *.log *.vdb *.vdb simv* *.key