题记:
还有一年就要毕业了,准备刷刷题,找工作。每天争取抽时间刷些题,欢迎交流~
- Day1 1~16
- Day2 16~24
- Day3 25~28
- Day4 29~35
- Vectorgates
题目:创建一个电路,这个电路含有两个3比特输入。对其分别做按位或,逻辑或和非。其中非的高三位由b提供,低三位由a提供。
代码部分
module top_module(
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise [2:0] = a[2:0] | b[2:0];// "|"是按位或
assign out_or_logical = a[2:0] || b [2:0];// "||"是逻辑或
assign out_not[5:3] = ~b[2:0];
assign out_not[2:0] = ~a[2:0];
endmodule
- Gates4
题目:创建一个四输入的电路,有三个输出:
- out_and
- out_or
- out_xor
代码部分
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[3] && in[2] && in[1] && in[0];
assign out_or = in[3] || in[2] || in[1] || in[0];
assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0];
endmodule
- 16 Vector3
部分选择(part selection),concatenation operator{a,b,c}用于连接向量
E.g. {3’b111, 3’b000} =>6’b111000
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );//
assign w[7:0] = {a[4:0],b[4:2]};
assign x[7:0] = {b[1:0],c[4:0],d[4]};
assign y[7:0] = {d[3:0],e[4:1]};
assign z[7:0] = {e[0],f[4:0],2'b11};
// assign { ... } = { ... };
endmodule
- 17 Vector reverse
8比特输出翻转
module top_module(
input [7:0] in,
output [7:0] out
);
assign out[7:0] = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
endmodule
注意:向量不能直接翻转,需要用链接符号{}依次进行翻转
- 18 Replication operator
复制一些比特位
E.g
{5{1'b1}} // 5'b11111 (or 5'd31 or 5'h1f)
{2{a,b,c}} // The same as {a,b,c,a,b,c}
{3'd5, {2{3'd6}}} // 9'b101_110_110. It's a concatenation of 101 with
// the second vector, which is two copies of 3'b110.
module top_module (
input [7:0] in,
output [31:0] out );//
// assign out = { replicate-sign-bit , the-input };
assign out[31:0] = {
{25{in[7]}}, in[6],in[5],in[4],in[3],in[2],in[1],in[0]};
endmodule
- 19 More Replication
module top_module (
input a, b, c, d, e,
output [24:0] out );//
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
// assign out = ~{ ... } ^ { ... };
assign out[24:0] = ~{
{5{a}},