N32G451CCL7芯片系统时钟设置内部PLL 128MHZ

系统供电3.3V，内部HSI时钟，倍频到128Mhz,SetSysClockToPLL(128000000,SYSCLK_PLLSRC_HSI);系统时钟分配如下所示：
SYSCLK: 128000000
HCLK  : 128000000
PCLK1 : 32000000
PCLK2 : 64000000
ADCPL : 128000000
ADCHL : 128000000
同样，前面是头文件代码，后面是应用代码，仅做记录，方便以后移植应用，代码已测试。

#ifndef __CLOCK_H__

#define __CLOCK_H__

#ifdef __cplusplus

extern "C" {

#endif

#include "main.h"

 

void SetSysClock_HSE_PLL(uint32_t RCC_PLLMULL);

void SetSysClockToHSI(void);

void SetSysClockToPLL(uint32_t freq, uint8_t src);

#ifdef __cplusplus

}

#endif

#endif

#include "clock.h"

 

void SetSysClock_HSE_PLL(uint32_t RCC_PLLMULL)

{

    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

    uint32_t Flash_Latency_Temp=0;

    uint32_t PLL_Temp=0;

    uint32_t System_Temp=0;

    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/

    /* Enable HSE */

    RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);

    /* Wait till HSE is ready and if Time out is reached exit */

    do

    {

       HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF;

       StartUpCounter++;

    } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

    if ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET)

    {

       HSEStatus = (uint32_t)0x01;

    }

    else

    {

       HSEStatus = (uint32_t)0x00;

    }

    if (HSEStatus == (uint32_t)0x01)

    {

       /* Enable Prefetch Buffer */

       FLASH->AC |= FLASH_AC_PRFTBFEN;

       /* Flash 2 wait state */

       Flash_Latency_Temp = FLASH->AC;

       Flash_Latency_Temp &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);

       Flash_Latency_Temp |= (uint32_t)FLASH_AC_LATENCY_4;

       FLASH->AC = Flash_Latency_Temp;

       /* HCLK = SYSCLK */

       RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;

       /* PCLK2 = HCLK */

       RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;

       /* PCLK1 = HCLK */

       RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;

       /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */

       PLL_Temp = RCC->CFG;

       PLL_Temp &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));

       PLL_Temp |= (uint32_t)(RCC_CFG_PLLSRC_HSE | RCC_PLLMULL);

       RCC->CFG = PLL_Temp;

       /* Enable PLL */

       RCC->CTRL |= RCC_CTRL_PLLEN;

       /* Wait till PLL is ready */

       while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0)

       {

       }

       /* Select PLL as system clock source */

       System_Temp = RCC->CFG;

       System_Temp &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));

       System_Temp |= (uint32_t)RCC_CFG_SCLKSW_PLL;

       RCC->CFG = System_Temp;

       /* Wait till PLL is used as system clock source */

       while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08)

       {

       }

    }

    else

    { /* If HSE fails to start-up, the application will have wrong clock

         configuration. User can add here some code to deal with this error */

    }

}

void SetSysClockToHSI(void)

{

    RCC_DeInit();

    RCC_EnableHsi(ENABLE);

    /* Enable Prefetch Buffer */

    FLASH_PrefetchBufSet(FLASH_PrefetchBuf_EN);

    /* Flash 0 wait state */

    FLASH_SetLatency(FLASH_LATENCY_0);

    /* HCLK = SYSCLK */

    RCC_ConfigHclk(RCC_SYSCLK_DIV1);

    /* PCLK2 = HCLK */

    RCC_ConfigPclk2(RCC_HCLK_DIV1);

    /* PCLK1 = HCLK */

    RCC_ConfigPclk1(RCC_HCLK_DIV1);

    /* Select HSE as system clock source */

    RCC_ConfigSysclk(RCC_SYSCLK_SRC_HSI);

    /* Wait till PLL is used as system clock source */

    while (RCC_GetSysclkSrc() != 0x00)

    {

    }

}

ErrorStatus HSEStartUpStatus;

void SetSysClockToPLL(uint32_t freq, uint8_t src)

{

    uint32_t pllsrc = (src == SYSCLK_PLLSRC_HSI ? RCC_PLL_SRC_HSI_DIV2 : RCC_PLL_SRC_HSE_DIV2);

    uint32_t pllmul;

    uint32_t latency;

    uint32_t pclk1div, pclk2div;

    if (HSE_VALUE != 8000000)

    {

        /* HSE_VALUE == 8000000 is needed in this project! */

        while (1)

            ;

    }

    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration

     * -----------------------------*/

    /* RCC system reset(for debug purpose) */

    RCC_DeInit();

    if (src == SYSCLK_PLLSRC_HSE)

    {

        /* Enable HSE */

        RCC_ConfigHse(RCC_HSE_ENABLE);

        /* Wait till HSE is ready */

        HSEStartUpStatus = RCC_WaitHseStable();

        if (HSEStartUpStatus != SUCCESS)

        {

            /* If HSE fails to start-up, the application will have wrong clock

               configuration. User can add here some code to deal with this

               error */

            /* Go to infinite loop */

            while (1)

                ;

        }

    }

    switch (freq)

    {

    case 24000000:

        latency  = FLASH_LATENCY_0;

        pllmul   = RCC_PLL_MUL_6;

        pclk1div = RCC_HCLK_DIV1;

        pclk2div = RCC_HCLK_DIV1;

        break;

    case 36000000:

        latency  = FLASH_LATENCY_1;

        pllmul   = RCC_PLL_MUL_9;

        pclk1div = RCC_HCLK_DIV1;

        pclk2div = RCC_HCLK_DIV1;

        break;

    case 48000000:

        latency  = FLASH_LATENCY_1;

        pllmul   = RCC_PLL_MUL_12;

        pclk1div = RCC_HCLK_DIV2;

        pclk2div = RCC_HCLK_DIV1;

        break;

    case 56000000:

        latency  = FLASH_LATENCY_1;

        pllmul   = RCC_PLL_MUL_14;

        pclk1div = RCC_HCLK_DIV2;

        pclk2div = RCC_HCLK_DIV1;

        break;

    case 72000000:

        latency  = FLASH_LATENCY_2;

        pllmul   = RCC_PLL_MUL_18;

        pclk1div = RCC_HCLK_DIV2;

        pclk2div = RCC_HCLK_DIV1;

        break;

    case 96000000:

        latency  = FLASH_LATENCY_2;

        pllmul   = RCC_PLL_MUL_24;

        pclk1div = RCC_HCLK_DIV4;

        pclk2div = RCC_HCLK_DIV2;

        break;

    case 128000000:

        latency  = FLASH_LATENCY_3;

        pllmul   = RCC_PLL_MUL_32;

        pclk1div = RCC_HCLK_DIV4;

        pclk2div = RCC_HCLK_DIV2;

        break;

    case 144000000:

        /* must use HSE as PLL source */

        latency  = FLASH_LATENCY_4;

        pllsrc   = RCC_PLL_SRC_HSE_DIV1;

        pllmul   = RCC_PLL_MUL_18;

        pclk1div = RCC_HCLK_DIV4;

        pclk2div = RCC_HCLK_DIV2;

        break;

    default:

        while (1)

            ;

    }

    FLASH_SetLatency(latency);

    /* HCLK = SYSCLK */

    RCC_ConfigHclk(RCC_SYSCLK_DIV1);

    /* PCLK2 = HCLK */

    RCC_ConfigPclk2(pclk2div);

    /* PCLK1 = HCLK */

    RCC_ConfigPclk1(pclk1div);

    RCC_ConfigPll(pllsrc, pllmul);

    /* Enable PLL */

    RCC_EnablePll(ENABLE);

    /* Wait till PLL is ready */

    while (RCC_GetFlagStatus(RCC_FLAG_PLLRD) == RESET)

        ;

    /* Select PLL as system clock source */

    RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLLCLK);

    /* Wait till PLL is used as system clock source */

    while (RCC_GetSysclkSrc() != 0x08)

        ;

}