开放点东西（AM3359）EtherCAT

    for (i=0; i < 10; i++)
        pRegPerm->reg_properties[i]= TIESC_PERM_READ_ONLY; 

    pRegPerm->reg_properties[0x10]= TIESC_PERM_RW;//Configured Station address
    pRegPerm->reg_properties[0x11]= TIESC_PERM_RW;//Configured Station address
    pRegPerm->reg_properties[0x12]= TIESC_PERM_READ_ONLY;//Configured Station alias
    pRegPerm->reg_properties[0x13]= TIESC_PERM_READ_ONLY;//Configured Station alias
    pRegPerm->reg_properties[0x100]= TIESC_PERM_RW;//DL control
    pRegPerm->reg_properties[0x101]= TIESC_PERM_RW;//DL control
    pRegPerm->reg_properties[0x102]= TIESC_PERM_READ_ONLY;//DL control
    pRegPerm->reg_properties[0x103]= TIESC_PERM_RW;//DL control
    pRegPerm->reg_properties[0x108]= TIESC_PERM_RW;//Physical RW offset
    pRegPerm->reg_properties[0x109]= TIESC_PERM_RW;//Physical RW offset
    pRegPerm->reg_properties[0x110]= TIESC_PERM_READ_ONLY;//ESC DL status
    pRegPerm->reg_properties[0x111]= TIESC_PERM_READ_ONLY;//ESC DL status
    pRegPerm->reg_properties[0x120]= TIESC_PERM_RW;//AL control
    pRegPerm->reg_properties[0x121]= TIESC_PERM_RW;//AL control
    pRegPerm->reg_properties[0x130]= TIESC_PERM_READ_ONLY;//ESC AL status
    pRegPerm->reg_properties[0x131]= TIESC_PERM_READ_ONLY;//ESC AL status
    pRegPerm->reg_properties[0x134]= TIESC_PERM_READ_ONLY;//ESC AL status code
    pRegPerm->reg_properties[0x135]= TIESC_PERM_READ_ONLY;//ESC AL status code    
    pRegPerm->reg_properties[0x140]= TIESC_PERM_READ_ONLY;//ESC PDI control
    pRegPerm->reg_properties[0x141]= TIESC_PERM_READ_ONLY;//ESC configuration
    pRegPerm->reg_properties[0x150]= TIESC_PERM_READ_ONLY;//Onchip configuration
    pRegPerm->reg_properties[0x151]= TIESC_PERM_READ_ONLY;//SYNC/LATCH PDI configuration
    pRegPerm->reg_properties[0x152]= TIESC_PERM_READ_ONLY;//Onchip extended configuration
    pRegPerm->reg_properties[0x153]= TIESC_PERM_READ_ONLY;//Onchip extended configuration
    pRegPerm->reg_properties[0x200]= TIESC_PERM_RW;//ECAT event mask
    pRegPerm->reg_properties[0x201]= TIESC_PERM_RW;//ECAT event mask
    pRegPerm->reg_properties[0x204]= TIESC_PERM_READ_ONLY;//AL event mask
    pRegPerm->reg_properties[0x205]= TIESC_PERM_READ_ONLY;//AL event mask
    pRegPerm->reg_properties[0x206]= TIESC_PERM_READ_ONLY;//AL event mask
    pRegPerm->reg_properties[0x207]= TIESC_PERM_READ_ONLY;//AL event mask
    pRegPerm->reg_properties[0x210]= TIESC_PERM_READ_ONLY;//ECAT event request
    pRegPerm->reg_properties[0x211]= TIESC_PERM_READ_ONLY;//ECAT event request
    pRegPerm->reg_properties[0x220]= TIESC_PERM_READ_ONLY;//AL event request
    pRegPerm->reg_properties[0x221]= TIESC_PERM_READ_ONLY;//AL event request
    pRegPerm->reg_properties[0x222]= TIESC_PERM_READ_ONLY;//AL event request
    pRegPerm->reg_properties[0x223]= TIESC_PERM_READ_ONLY;//AL event request
    pRegPerm->reg_properties[0x300]= TIESC_PERM_RW;//Invalid frame counter Port0
    pRegPerm->reg_properties[0x301]= TIESC_PERM_RW;//RX_ERR counter Port0
    pRegPerm->reg_properties[0x302]= TIESC_PERM_RW;//Invalid frame counter Port1
    pRegPerm->reg_properties[0x303]= TIESC_PERM_RW;//RX_ERR counter Port1
    pRegPerm->reg_properties[0x304]= TIESC_PERM_READ_ONLY;//Invalid frame counter Port2
    pRegPerm->reg_properties[0x305]= TIESC_PERM_READ_ONLY;//RX_ERR counter Port2
    pRegPerm->reg_properties[0x306]= TIESC_PERM_READ_ONLY;//Invalid frame counter Port3
    pRegPerm->reg_properties[0x307]= TIESC_PERM_READ_ONLY;//RX_ERR counter Port3
    pRegPerm->reg_properties[0x308]= TIESC_PERM_RW;//Forwarded Error Port0
    pRegPerm->reg_properties[0x309]= TIESC_PERM_RW;//Forwarded Error Port1
    pRegPerm->reg_properties[0x30A]= TIESC_PERM_READ_ONLY;//Forwarded Error Port2
    pRegPerm->reg_properties[0x30B]= TIESC_PERM_READ_ONLY;//Forwarded Error Port3
    pRegPerm->reg_properties[0x30C]= TIESC_PERM_RW;//ECAT processing unit counter
    pRegPerm->reg_properties[0x310]= TIESC_PERM_RW;//Link lost counter Port0
    pRegPerm->reg_properties[0x311]= TIESC_PERM_RW;//Link lost counter Port1
    pRegPerm->reg_properties[0x312]= TIESC_PERM_READ_ONLY;//Link lost counter Port2
    pRegPerm->reg_properties[0x313]= TIESC_PERM_READ_ONLY;//Link lost counter Port3
    pRegPerm->reg_properties[0x400]= TIESC_PERM_RW;//Watchdog divider
    pRegPerm->reg_properties[0x401]= TIESC_PERM_RW;//Watchdog divider
    pRegPerm->reg_properties[0x410]= TIESC_PERM_RW;//Watchdog time PDI
    pRegPerm->reg_properties[0x411]= TIESC_PERM_RW;//Watchdog time PDI
    pRegPerm->reg_properties[0x420]= TIESC_PERM_RW;//Watchdog time PD
    pRegPerm->reg_properties[0x421]= TIESC_PERM_RW;//Watchdog time PD
    pRegPerm->reg_properties[0x440]= TIESC_PERM_READ_ONLY;//Watchdog process data
    pRegPerm->reg_properties[0x441]= TIESC_PERM_READ_ONLY;//Watchdog process data
    pRegPerm->reg_properties[0x442]= TIESC_PERM_RW;//Watchdog counter PD
    pRegPerm->reg_properties[0x443]= TIESC_PERM_RW;//Watchdog counter PDI
    pRegPerm->reg_properties[0x500]= TIESC_PERM_RW;//EEPROM configuration
    pRegPerm->reg_properties[0x501]= TIESC_PERM_READ_ONLY;//EEPROM PDI access state
   for(i=0; i < 8; i++)
        pRegPerm->reg_properties[0x502+i]= TIESC_PERM_RW;
    for (i=0; i < 8; i++) //8 FMMUs
    {
        memset((void*)&pRegPerm->reg_properties[0x600+i*16], TIESC_PERM_RW, 13);
        memset((void*)&pRegPerm->reg_properties[0x60D+i*16], TIESC_PERM_READ_ONLY, 3);//Mark reserved bytes read only
    }

    for (i=0; i < 8; i++) //8 SMs
    {
        memset((void*)&pRegPerm->reg_properties[0x800+i*8], TIESC_PERM_RW, 5);
        memset((void*)&pRegPerm->reg_properties[0x805+i*8], TIESC_PERM_READ_ONLY, 1);
        memset((void*)&pRegPerm->reg_properties[0x806+i*8], TIESC_PERM_RW, 1);
        memset((void*)&pRegPerm->reg_properties[0x807+i*8], TIESC_PERM_READ_ONLY, 1);
    }

   for (i=0; i < 4; i++)
        pRegPerm->reg_properties[0x900+i]= TIESC_PERM_RW;

    for (i=0; i < 12; i++)
        pRegPerm->reg_properties[0x904+i]= TIESC_PERM_READ_ONLY;

    for (i=0; i < 4; i++)
        pRegPerm->reg_properties[0x910+i]= TIESC_PERM_RW;
    for (i=0; i < 4; i++)
        pRegPerm->reg_properties[0x914+i]= TIESC_PERM_READ_ONLY;	

    for (i=0; i < 8; i++)
        pRegPerm->reg_properties[0x918+i]= TIESC_PERM_READ_ONLY;

    for (i=0; i < 12; i++)
        pRegPerm->reg_properties[0x920+i]= TIESC_PERM_RW;
  pRegPerm->reg_properties[0x92C]= TIESC_PERM_READ_ONLY;//System Time Difference
    pRegPerm->reg_properties[0x92D]= TIESC_PERM_READ_ONLY;//System Time Difference
    pRegPerm->reg_properties[0x92E]= TIESC_PERM_READ_ONLY;//System Time Difference
    pRegPerm->reg_properties[0x92F]= TIESC_PERM_READ_ONLY;//System Time Difference

    pRegPerm->reg_properties[0x930]= TIESC_PERM_RW;//Speed counter Start
    pRegPerm->reg_properties[0x931]= TIESC_PERM_RW;//Speed counter Start

    pRegPerm->reg_properties[0x932]= TIESC_PERM_READ_ONLY;//Speed counter Diff
    pRegPerm->reg_properties[0x933]= TIESC_PERM_READ_ONLY;//Speed counter Diff

    pRegPerm->reg_properties[0x934]= TIESC_PERM_RW;//System Time Difference Filter Depth
    pRegPerm->reg_properties[0x935]= TIESC_PERM_RW;//Speed counter Filter Depth

    pRegPerm->reg_properties[0x981]= TIESC_PERM_RW;//Sync Activation

	
    pRegPerm->reg_properties[0x982]= TIESC_PERM_READ_ONLY;//Pulse length of Sync Signals
    pRegPerm->reg_properties[0x983]= TIESC_PERM_READ_ONLY;//Pulse length of Sync Signals
    pRegPerm->reg_properties[0x984]= TIESC_PERM_READ_ONLY;//SYNC Activation status
    pRegPerm->reg_properties[0x98E]= TIESC_PERM_READ_ONLY;//SYNC0 status
    pRegPerm->reg_properties[0x98F]= TIESC_PERM_READ_ONLY;//SYNC1 status
    for (i=0; i < 8; i++)
        pRegPerm->reg_properties[0x990+i]= TIESC_PERM_RW;
    for (i=0; i < 8; i++)
        pRegPerm->reg_properties[0x998+i]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 10; i++)
        pRegPerm->reg_properties[0x9A0+i]= TIESC_PERM_RW;
    for (i=0; i < 34; i++)
        pRegPerm->reg_properties[0x9AE+i]= TIESC_PERM_READ_ONLY;
#endif   
    //TI vendor specific registers
    for (i=0; i < 11; i++)
        pRegPerm->reg_properties[0xE00+i]= TIESC_PERM_READ_ONLY;
    
    pRegPerm->reg_properties[0xE10]= TIESC_PERM_RW;
    pRegPerm->reg_properties[0xE11]= TIESC_PERM_RW;
    
    pRegPerm->reg_properties[0xE12]= TIESC_PERM_RW;
    pRegPerm->reg_properties[0xE13]= TIESC_PERM_RW;
    
    pRegPerm->reg_properties[0xE14]= TIESC_PERM_RW;
    pRegPerm->reg_properties[0xE15]= TIESC_PERM_RW;
    pRegPerm->reg_properties[0xE16]= TIESC_PERM_RW;
    
    pRegPerm->reg_properties[0xEE0]= TIESC_PERM_RW;//APP_RELOAD_FLAG_REG
#ifdef ENABLE_PDI_REG_PERMISSIONS
    memset(&pdi_reg_perm_array[0], 3, 4096);
    
    for (i=0; i < 10; i++)
        pdi_reg_perm_array[i]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x10]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x12]= TIESC_PERM_RW;
    for (i=0; i < 4; i++)
        pdi_reg_perm_array[i+0x100]= TIESC_PERM_READ_ONLY;	
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x108]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x110]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x120]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x130]= TIESC_PERM_RW;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x134]= TIESC_PERM_RW;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x140]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 4; i++)
        pdi_reg_perm_array[i+0x150]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x200]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 4; i++)
        pdi_reg_perm_array[i+0x204]= TIESC_PERM_RW;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x210]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 4; i++)
        pdi_reg_perm_array[i+0x220]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 13; i++)
        pdi_reg_perm_array[i+0x300]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 4; i++)
        pdi_reg_perm_array[i+0x310]= TIESC_PERM_READ_ONLY;	
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x400]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x410]= TIESC_PERM_READ_ONLY;	
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x420]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 4; i++)
        pdi_reg_perm_array[i+0x440]= TIESC_PERM_READ_ONLY;
	
    pdi_reg_perm_array[0x500]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 15; i++)
        pdi_reg_perm_array[i+0x501]= TIESC_PERM_RW;
    pdi_reg_perm_array[0x510]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 6; i++)
        pdi_reg_perm_array[i+0x511]= TIESC_PERM_RW;    
    pdi_reg_perm_array[0x516]= TIESC_PERM_READ_ONLY;
    pdi_reg_perm_array[0x517]= TIESC_PERM_RW;    
    for (i=0; i < 8; i++) //8 FMMUs
    {
        memset((void*)&pdi_reg_perm_array[0x600+i*16], TIESC_PERM_READ_ONLY, 16);
    }

    for (i=0; i < 8; i++) //8 SMs
    {
        memset((void*)&pdi_reg_perm_array[0x800+i*8], TIESC_PERM_READ_ONLY, 7);
        memset((void*)&pdi_reg_perm_array[0x807+i*8], TIESC_PERM_RW, 1);
    }
    for (i=0; i < 27; i++)
        pdi_reg_perm_array[i+0x900]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 22; i++)
        pdi_reg_perm_array[i+0x920]= TIESC_PERM_READ_ONLY;	
	
    pdi_reg_perm_array[0x981]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x982]= TIESC_PERM_RW;
	
    pdi_reg_perm_array[0x984]= TIESC_PERM_READ_ONLY;  	
    for (i=0; i < 2; i++)
        pdi_reg_perm_array[i+0x98E]= TIESC_PERM_READ_ONLY;	
    for (i=0; i < 26; i++)
        pdi_reg_perm_array[i+0x990]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 34; i++)
        pdi_reg_perm_array[i+0x9AE]= TIESC_PERM_READ_ONLY;
    for (i=0; i < 11; i++)
        pdi_reg_perm_array[i+0xE00]= TIESC_PERM_READ_ONLY;        
    
    pdi_reg_perm_array[0xE10]= TIESC_PERM_RW;
    pdi_reg_perm_array[0xE11]= TIESC_PERM_RW;
    
    pdi_reg_perm_array[0xE12]= TIESC_PERM_RW;
    pdi_reg_perm_array[0xE13]= TIESC_PERM_RW;
    
    pdi_reg_perm_array[0xE14]= TIESC_PERM_RW;
    pdi_reg_perm_array[0xE15]= TIESC_PERM_RW;
    pdi_reg_perm_array[0xE16]= TIESC_PERM_RW;   
    pdi_reg_perm_array[0xE17]= TIESC_PERM_RW;