(1) uvm_tlm_analysis_fifo中的*_export,虽然名字中有export,但是本质上都是IMP.
(2) uvm_tlm_analysis_fifo内的缓冲使用system verilog中的mailbox实现;
(3)需要补充fifo的相关函数,如put,get,try_put,try_get;
在FIFO里面实现了get函数和set函数:因此定义了对应的port可以直接调用get函数,put函数
class my_env extends uvm_env;
//3个fifo
uvm_tlm_analysis_fifo#(my_transaction) iagt_mdl_fifo;
uvm_tlm_analysis_fifo#(my_transaction) oagt_scb_fifo;
uvm_tlm_analysis_fifo#(my_transaction) mdl_scb_fifo;
endclass
function void my_env:: build_phase(uvm_phase phas