FPGA-CD4015

一、CD4015芯片介绍

CD4015是COMS双路4级静态移位寄存器的串行输入，并行输出的移位寄存器。芯片引脚图，电路图和真值表如下图。

二、代码

1、D触发器代码（子模块）

module d_cfq(CP,MR,D,Q);
input CP,MR,D;
output Q;

reg Q;

always @(posedge CP or negedge MR)
  begin
    if(MR == 0)
      Q <= D;
    else if(MR == 1)
      Q <= 0;
  end

endmodule

2、顶层模块

module dcmk(CP,MR,D,Q0,Q1,Q2,Q3);
input CP,MR,D;
output Q0,Q1,Q2,Q3;

wire Q0,Q1,Q2,Q3;

d_cfq u1(CP,MR,D,Q0);
d_cfq u2(CP,MR,Q0,Q1);
d_cfq u3(CP,MR,Q1,Q2);
d_cfq u4(CP,MR,Q2,Q3);

endmodule

3、仿真代码

`timescale 1ns / 1ps

module dcmk_fz;
reg CP,MR,D;
wire Q0,Q1,Q2,Q3;

dcmk u1(.CP(CP),
        .MR(MR),
        .D(D),
        .Q0(Q0),
        .Q1(Q1),
        .Q2(Q2),
        .Q3(Q3)
        );

initial
  begin
    CP <= 0;
    
    while(1) #5 CP <= ~CP;
  end

initial
  begin
    MR <= 1;
    
    #20 MR <= 0;
  end
  
initial
  begin
    D <= 0;
    
    #10 D <= 1;
    #10 D <= 1;
    #10 D <= 1;
    #10 D <= 1;
    #10 D <= 1;
    #10 D <= 1;
    #10 D <= 1;
    #10 D <= 1;
    #10 D <= 0;
    #10 D <= 0;
    #10 D <= 1;
    #10 D <= 1;
    #10 D <= 0;
    #10 D <= 0;
    #10 D <= 1;
    #10 D <= 1;
    #10 D <= 0;
    #10 D <= 0;
    #10 D <= 0;
    #10 D <= 0;
  end

endmodule

三、运行与调试

1、RTL实图

2、仿真图