Quartus: Cannot convert all sets of registers into RAM megafunctions when creating nodes.

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已于 2022-12-12 14:44:51 修改

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文章标签： verilog fpga开发 systemverilog 硬件工程

于 2022-12-12 14:36:30 首次发布

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Error (276003): Cannot convert all sets of registers into RAM megafunctions when creating nodes. The resulting number of registers remaining in design exceeds the number of registers in the device or the number specified by the assignment max_number_of_registers_from_uninferred_rams. This can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis

在代码中直接例化了大面积的memory，期待Quatus综合工具能直接自动综合成block ram，结果报了上述错误，但可以确认使用RAM资源没有超过所选芯片上限。找到官方的解释如下：

Quartus II Message Help v13.0

官方提到两种原因，第二种提示 max_number_of_registers_from_uninferred_rams 可能设置不对，但该值default为-1，即无限制，检查发现设置正确。

第一种原因提示代码风格可能综合工具不识别，找到官方的suggested coding styles ：

1. Recommended HDL Coding Styles

此处使用了Single-Clock, Simple Dual-Port Synchronous RAM with New Data Read-During-Write Behavior，示例代码如下：

1.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write...

module single_clock_wr_ram(
    output reg [7:0] q,
    input [7:0] d,
    input [6:0] write_address, read_address,
    input we, clk
);
    reg [7:0] mem [127:0];

    always @ (posedge clk) begin
        if (we)
            mem[write_address] = d;
        q = mem[read_address]; // q does get d in this clock 
                               // cycle if we is high
    end
endmodule

重新修改代码风格后编译通过。