System Verilog syntax Error--数据类型

Union 

Error-[PUMSS] Incorrect packed union members size

Packed union members must have same size

Error-[USVSUU] Unsupported System Verilog construct

默认情况为unpacked的,VCS不支持编译unpacked的 union

Unpacked unions are not yet supported

//typedef union{   //❌，VCS不支持
typedef union packed{//👌
    //bit [15:0] buf_a; //❌ 联合体成员buf_a和buf_b size须相同
    bit [7:0] buf_a;//👌
    bit [7:0] buf_b;  
} data_u;

array

Error-[UMPSU] Unpacked member

Packed structure 'io_tx_wqe' contains unpacked members

  typedef struct packed {
        bit [31:0] buf_addr_hi;
        bit [31:0] buf_addr_lo;
    } io_tx_buf_desc;

    typedef struct packed {
        io_tx_buf_desc [2:0] sgl;  //👌
        //io_tx_buf_desc  sgl[3];  //❌
        bit [7:0] aa;
    } io_tx_wqe;

合并数组：io_tx_buf_desc [2:0] sgl;

非合并数组：io_tx_buf_desc  sgl[3];