[011] [ARM-Cortex-M3/4] CM3指令集与CMSIS函数汇总

1 指令集

Mnemonic	Operands	Brief description	Flags	See
ADC, ADCS	{Rd,} Rn, Op2	Add with Carry	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
ADD, ADDS	{Rd,} Rn, Op2	Add	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
ADD, ADDW	{Rd,} Rn, #imm12	Add	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
ADR	Rd, label	Load PC-relative Address	-	ADR
AND, ANDS	{Rd,} Rn, Op2	Logical AND	N,Z,C	AND, ORR, EOR, BIC, and ORN
ASR, ASRS	Rd, Rm, <Rs|#n>	Arithmetic Shift Right	N,Z,C	ASR, LSL, LSR, ROR, and RRX
B	label	Branch	-	B, BL, BX, and BLX
BFC	Rd, #lsb, #width	Bit Field Clear	-	BFC and BFI
BFI	Rd, Rn, #lsb, #width	Bit Field Insert	-	BFC and BFI
BIC, BICS	{Rd,} Rn, Op2	Bit Clear	N,Z,C	AND, ORR, EOR, BIC, and ORN
BKPT	#imm	Breakpoint	-	BKPT
BL	label	Branch with Link	-	B, BL, BX, and BLX
BLX	Rm	Branch indirect with Link	-	B, BL, BX, and BLX
BX	Rm	Branch indirect	-	B, BL, BX, and BLX
CBNZ	Rn, label	Compare and Branch if Non Zero	-	CBZ and CBNZ
CBZ	Rn, label	Compare and Branch if Zero	-	CBZ and CBNZ
CLREX	-	Clear Exclusive	-	CLREX
CLZ	Rd, Rm	Count Leading Zeros	-	CLZ
CMN	Rn, Op2	Compare Negative	N,Z,C,V	CMP and CMN
CMP	Rn, Op2	Compare	N,Z,C,V	CMP and CMN
CPSID	i	Change Processor State, Disable Interrupts	-	CPS
CPSIE	i	Change Processor State, Enable Interrupts	-	CPS
DMB	-	Data Memory Barrier	-	DMB
DSB	-	Data Synchronization Barrier	-	DSB
EOR, EORS	{Rd,} Rn, Op2	Exclusive OR	N,Z,C	AND, ORR, EOR, BIC, and ORN
ISB	-	Instruction Synchronization Barrier	-	ISB
IT	-	If-Then condition block	-	IT
LDM	Rn{!}, reglist	Load Multiple registers, increment after	-	LDM and STM
LDMDB, LDMEA	Rn{!}, reglist	Load Multiple registers, decrement before	-	LDM and STM
LDMFD, LDMIA	Rn{!}, reglist	Load Multiple registers, increment after	-	LDM and STM
LDR	Rt, [Rn, #offset]	Load Register with word	-	Memory access instructions
LDRB, LDRBT	Rt, [Rn, #offset]	Load Register with byte	-	Memory access instructions
LDRD	Rt, Rt2, [Rn, #offset]	Load Register with two bytes	-	LDR and STR, immediate offset
LDREX	Rt, [Rn, #offset]	Load Register Exclusive	-	LDREX and STREX
LDREXB	Rt, [Rn]	Load Register Exclusive with Byte	-	LDREX and STREX
LDREXH	Rt, [Rn]	Load Register Exclusive with Halfword	-	LDREX and STREX
LDRH, LDRHT	Rt, [Rn, #offset]	Load Register with Halfword	-	Memory access instructions
LDRSB, LDRSBT	Rt, [Rn, #offset]	Load Register with Signed Byte	-	Memory access instructions
LDRSH, LDRSHT	Rt, [Rn, #offset]	Load Register with Signed Halfword	-	Memory access instructions
LDRT	Rt, [Rn, #offset]	Load Register with word	-	Memory access instructions
LSL, LSLS	Rd, Rm, <Rs|#n>	Logical Shift Left	N,Z,C	ASR, LSL, LSR, ROR, and RRX
LSR, LSRS	Rd, Rm, <Rs|#n>	Logical Shift Right	N,Z,C	ASR, LSL, LSR, ROR, and RRX
MLA	Rd, Rn, Rm, Ra	Multiply with Accumulate, 32-bit result	-	MUL, MLA, and MLS
MLS	Rd, Rn, Rm, Ra	Multiply and Subtract, 32-bit result	-	MUL, MLA, and MLS
MOV, MOVS	Rd, Op2	Move	N,Z,C	MOV and MVN
MOVT	Rd, #imm16	Move Top	-	MOVT
MOVW, MOV	Rd, #imm16	Move 16-bit constant	N,Z,C	MOV and MVN
MRS	Rd, spec_reg	Move from Special Register to general register	-	MRS
MSR	spec_reg, Rm	Move from general register to Special Register	N,Z,C,V	MSR
MUL, MULS	{Rd,} Rn, Rm	Multiply, 32-bit result	N,Z	MUL, MLA, and MLS
MVN, MVNS	Rd, Op2	Move NOT	N,Z,C	MOV and MVN
NOP	-	No Operation	-	NOP
ORN, ORNS	{Rd,} Rn, Op2	Logical OR NOT	N,Z,C	AND, ORR, EOR, BIC, and ORN
ORR, ORRS	{Rd,} Rn, Op2	Logical OR	N,Z,C	AND, ORR, EOR, BIC, and ORN
POP	reglist	Pop registers from stack	-	PUSH and POP
PUSH	reglist	Push registers onto stack	-	PUSH and POP
RBIT	Rd, Rn	Reverse Bits	-	REV, REV16, REVSH, and RBIT
REV	Rd, Rn	Reverse byte order in a word	-	REV, REV16, REVSH, and RBIT
REV16	Rd, Rn	Reverse byte order in each halfword	-	REV, REV16, REVSH, and RBIT
REVSH	Rd, Rn	Reverse byte order in bottom halfword and sign extend	-	REV, REV16, REVSH, and RBIT
ROR, RORS	Rd, Rm, <Rs|#n>	Rotate Right	N,Z,C	ASR, LSL, LSR, ROR, and RRX
RRX, RRXS	Rd, Rm	Rotate Right with Extend	N,Z,C	ASR, LSL, LSR, ROR, and RRX
RSB, RSBS	{Rd,} Rn, Op2	Reverse Subtract	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
SBC, SBCS	{Rd,} Rn, Op2	Subtract with Carry	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
SBFX	Rd, Rn, #lsb, #width	Signed Bit Field Extract	-	SBFX and UBFX
SDIV	{Rd,} Rn, Rm	Signed Divide	-	SDIV and UDIV
SEV	-	Send Event	-	SEV
SMLAL	RdLo, RdHi, Rn, Rm	Signed Multiply with Accumulate (32 x 32 + 64), 64-bit result	-	UMULL, UMLAL, SMULL, and SMLAL
SMULL	RdLo, RdHi, Rn, Rm	Signed Multiply (32 x 32), 64-bit result	-	UMULL, UMLAL, SMULL, and SMLAL
SSAT	Rd, #n, Rm {,shift #s}	Signed Saturate	Q	SSAT and USAT
STM	Rn{!}, reglist	Store Multiple registers, increment after	-	LDM and STM
STMDB, STMEA	Rn{!}, reglist	Store Multiple registers, decrement before	-	LDM and STM
STMFD, STMIA	Rn{!}, reglist	Store Multiple registers, increment after	-	LDM and STM
STR	Rt, [Rn, #offset]	Store Register word	-	Memory access instructions
STRB, STRBT	Rt, [Rn, #offset]	Store Register byte	-	Memory access instructions
STRD	Rt, Rt2, [Rn, #offset]	Store Register two words	-	LDR and STR, immediate offset
STREX	Rd, Rt, [Rn, #offset]	Store Register Exclusive	-	LDREX and STREX
STREXB	Rd, Rt, [Rn]	Store Register Exclusive Byte	-	LDREX and STREX
STREXH	Rd, Rt, [Rn]	Store Register Exclusive Halfword	-	LDREX and STREX
STRH, STRHT	Rt, [Rn, #offset]	Store Register Halfword	-	Memory access instructions
STRT	Rt, [Rn, #offset]	Store Register word	-	Memory access instructions
SUB, SUBS	{Rd,} Rn, Op2	Subtract	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
SUB, SUBW	{Rd,} Rn, #imm12	Subtract	N,Z,C,V	ADD, ADC, SUB, SBC, and RSB
SVC	#imm	Supervisor Call	-	SVC
SXTB	{Rd,} Rm {,ROR #n}	Sign extend a byte	-	SXT and UXT
SXTH	{Rd,} Rm {,ROR #n}	Sign extend a halfword	-	SXT and UXT
TBB	[Rn, Rm]	Table Branch Byte	-	TBB and TBH
TBH	[Rn, Rm, LSL #1]	Table Branch Halfword	-	TBB and TBH
TEQ	Rn, Op2	Test Equivalence	N,Z,C	TST and TEQ
TST	Rn, Op2	Test	N,Z,C	TST and TEQ
UBFX	Rd, Rn, #lsb, #width	Unsigned Bit Field Extract	-	SBFX and UBFX
UDIV	{Rd,} Rn, Rm	Unsigned Divide	-	SDIV and UDIV
UMLAL	RdLo, RdHi, Rn, Rm	Unsigned Multiply with Accumulate (32 x 32 + 64), 64-bit result	-	UMULL, UMLAL, SMULL, and SMLAL
UMULL	RdLo, RdHi, Rn, Rm	Unsigned Multiply (32 x 32), 64-bit result	-	UMULL, UMLAL, SMULL, and SMLAL
USAT	Rd, #n, Rm {,shift #s}	Unsigned Saturate	Q	SSAT and USAT
UXTB	{Rd,} Rm {,ROR #n}	Zero extend a Byte	-	SXT and UXT
UXTH	{Rd,} Rm {,ROR #n}	Zero extend a Halfword	-	SXT and UXT
WFE	-	Wait For Event	-	WFE
WFI	-	Wait For Interrupt	-	WFI

2 CMSIS函数

Instruction	CMSIS function
CPSIE I	void __enable_irq(void)
CPSID I	void __disable_irq(void)
CPSIE F	void __enable_fault_irq(void)
CPSID F	void __disable_fault_irq(void)
ISB	void __ISB(void)
DSB	void __DSB(void)
DMB	void __DMB(void)
REV	uint32_t __REV(uint32_t int value)
REV16	uint32_t __REV16(uint32_t int value)
REVSH	uint32_t __REVSH(uint32_t int value)
RBIT	uint32_t __RBIT(uint32_t int value)
SEV	void __SEV(void)
WFE	void __WFE(void)
WFI	void __WFI(void)

▲ CMSIS functions to generate some Cortex-M3 instructions
使用`MRS`和`MSR`指令访问特殊寄存器的函数：

Special register	Access	CMSIS function
PRIMASK	Read	uint32_t __get_PRIMASK (void)
	Write	void __set_PRIMASK (uint32_t value)
FAULTMASK	Read	uint32_t __get_FAULTMASK(void)
	Write	void __set_FAULTMASK (uint32_t value)
BASEPRI	Read	uint32_t __get_BASEPRI (void)
	Write	void __set_BASEPRI (uint32_t value)
CONTROL	Read	uint32_t __get_CONTROL (void)
	Write	void __set_CONTROL (uint32_t value)
MSP	Read	uint32_t __get_MSP (void)
	Write	void __set_MSP (uint32_t TopOfMainStack)
PSP	Read	uint32_t __get_PSP (void)
	Write	void __set_PSP (uint32_t TopOfProcStack)

▲ CMSIS functions to access the special registers

END