Xilinx MicroBlaze 告警提示解决方案

告警： [BD 41-2559] AXI interface port /M02_AXI_0 is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port in an external clock port. If no external clock port exists in the design, make the source clock port /clk_wiz_1/clk_out1 external and associate the interface port to it.
 

解决：创建一个输出型的Port，连接到MicroBlaze的Clock上，如下图选择S_AXI_CLK。