全志A20看门狗watchdog调试

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本文链接:https://blog.csdn.net/kuangdoushi/article/details/78792324
全志的芯片手册里面watchdog只有两个寄存器:WDOG_CTRL_REG和WDOG_MODE_REG
从我的调试结果来看
WDOG_CTRL_REG设置好像无法生效,改进方法是在喂狗时先关闭狗,再喂狗,再使能狗
①wdt_enable(false);
②然后再喂狗;

③wdt_enable(true);


驱动修改如下:

static ssize_t sunxi_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos)
{
	printk("write:\n");

	/* See if we got the magic character 'V' and reload the timer */
	if(len) 
	{
		if(!g_nowayout) 
		{
			size_t i;

			/* in case it was set long ago */
			expect_release = false;

			/* scan to see whether or not we got the magic character */
			for(i = 0; i != len; i++) {
				char c;
				if(get_user(c, data + i))
					return -EFAULT;
				if(c == 'V')
				{
					printk("cyl: got V\n");
					//expect_release = true;
				}
			}
		}
		/* someone wrote to us, we should reload the timer */
+       wdt_enable(false);
		watchdog_kick();
+ 		wdt_enable(true);
	}
	return len;
}


应用程序如下:

#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
int main(void)
{
	int fd = open("/dev/watchdog", O_WRONLY);
	int ret = 0;
	int cnt = 0;
	if (fd == -1) {
		perror("watchdog");
		exit(EXIT_FAILURE);
	}
	while (1) {
		ret = write(fd, "V", 1);
		if (ret != 1) {
			ret = -1;
			break;
		}
		sleep(1);
		cnt++;
		if(cnt > 100)
		{
			printf("end end end end \n");
			break;
		}
		else
		{
			printf("cnt = %d \n", cnt);
			
		}
		
	}
	while(1)
	{
		printf("%d \n", cnt++);
		sleep(1);
	}
	close(fd);
	return ret;
}

注意:
此方法是我在喂狗无效后,实在没有办法的情况下做的。如果有人有更好的方法,请给我留言分享。谢谢!



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// Highrn //ret = mt9p031_set_output_control(sd, 0,2);rn mdelay(50);rn ret |= mt9p031_reg_write(client, 0x0d, 0x0000); // Lowrn mdelay(50);rnrn ret |= mt9p031_reg_write(client, 0x10, 0x0051); // PLL_CTRL; power up pllrn// ret |= mt9p031_reg_write(client, REG_MT9P031_PLL_CONF1, 0x1801); // PLL_CONFIG_1: m=24, n=1rn// ret |= mt9p031_reg_write(client, REG_MT9P031_PLL_CONF2, 0x0002); // PLL_CONFIG_2: p1=2, p2=0rn ret |= mt9p031_reg_write(client, 0x11, (MT9P031_PLL_M << 8) | (MT9P031_PLL_N - 1));rn ret |= mt9p031_reg_write(client, 0x12, MT9P031_PLL_P1 - 1);rn mdelay(10); //wait 10 ms for VCO to lockrn ret |= mt9p031_reg_write(client, 0x10, 0x0053); // PLL_CONTROL; use PLLrn mdelay(200);rnrn ret |= mt9p031_reg_write(client, 0x70, 0x0079); // RESERVED_CORE_70[/code]rnrnrn大神们,求解 论坛

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