FPGA如何产生自复位信号

二、自复位信号
module RST_INER(
clk_100M,

Rst_n
);

input clk_100M;
output Rst_n;
//==============================================================
wire clk_100M;
reg Rst_n;
//==============================================================
parameter INNER_CNT_END=9’d128;
reg [8:0] rst_inner_cnt;
always @(posedge clk_100M)
if(rst_inner_cnt<INNER_CNT_END)begin
rst_inner_cnt <= rst_inner_cnt +1’d1;
end else if(rst_inner_cntINNER_CNT_END) begin
rst_inner_cnt <= rst_inner_cnt;
end else begin
rst_inner_cnt <=0;
end
//============================================================
always @(posedge clk_100M)
if(rst_inner_cntINNER_CNT_END) begin
Rst_n <= 1;
end else begin
Rst_n <= 0;
end
//============================================================

endmodule

上电之后，通过计数器控制复位信号Rst_n的转换。