library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;
library WORK;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port(
clk : in std_logic;
rst : out std_logic
);
end top;
architecture Behavioral of top is
signal rst_vector : std_logic_vector(15 downto 0):=(other=>'1');
rst_after_power_on: process(clk)
begin
rst_vector <= '0' & rst_vector(15 downto 1);
end procrss rst_after_power_on;
rst <= rst_vector(0);
end Behavioral;