【DV】常用读写register通用 task

1. 读写memory

   read task (可传入address，仍然是利用ral model handle)

virtual task ral_access_read(input uvm_reg_block ral_blk,output uvm_state_e status,input bit[31：0] addr , output bit[31:0] data);

  uvm_sequence_base  seq;
  uvm_sequence_item  bus_req;
  uvm_sequencer_base sequencer;
  int unsigned       bus_width;
  uvm_reg_bus_op     rw_access;
  uvm_reg_map        maps[$];
  uvm_reg_adapter    adapter;

  seq = new();
  ral_blk.get_maps(maps);
  adapter = maps[0].get_adapter();
  sequencer = maps[0].get_sequencer();
  bus_width = maps[0].get_n_bytes();
  
  rw_access.kind = UVM_READ;
  rw_access.addr = addr;

  bus_req= adapter.reg2bus(rw_access);
  bus_req.set_sequencer(sequencer);

  seq.start_item(bus_req);
  seq.finish_item(bus_req);
  bus_req.end_event.wait_on();

  if(adapter.provides_responses)begin
    uvm_sequence_item bus_rsp;
    uvm_access_e op;
    seq.get_base_response(bus_rsp);
    adapter.bus2reg(bus_rsp,rw_access);
  end
  else
    adapter.bus2reg(bus_req,rw_access);

  data = rw_access.data & ((1<<bus_width*8)-1);
  status = rw_access.status;
endtask

write task 

virtual task ral_access_write(input uvm_reg_block ral_blk,output uvm_state_e status,input bit[31：0] addr , bit[31:0] data);

  uvm_sequence_base  seq;
  uvm_sequence_item  bus_req;
  uvm_sequencer_base sequencer;
  int unsigned       bus_width;
  uvm_reg_bus_op     rw_access;
  uvm_reg_map        maps[$];
  uvm_reg_adapter    adapter;

  seq = new();
  ral_blk.get_maps(maps);
  adapter = maps[0].get_adapter();
  sequencer = maps[0].get_sequencer();
  bus_width = maps[0].get_n_bytes();
  
  rw_access.kind = UVM_WRITE;
  rw_access.addr = addr;
  rw_access.data = data;

  bus_req= adapter.reg2bus(rw_access);
  bus_req.set_sequencer(sequencer);

  seq.start_item(bus_req);
  seq.finish_item(bus_req);
  bus_req.end_event.wait_on();

  if(adapter.provides_responses)begin
    uvm_sequence_item bus_rsp;
    uvm_access_e op;
    seq.get_base_response(bus_rsp);
    adapter.bus2reg(bus_rsp,rw_access);
  end
  else
    adapter.bus2reg(bus_req,rw_access);

  status = rw_access.status;
endtask

  第二种则是利用 bus sequencer 来访问

  

class reg_seq extends uvm_sequence #(apb_trans);

  apb_trans   apb_tr;
  apb_master_sequencer  seqr;
  ...

  virtual task body();
    if(!uvm_config_db#(apb_master_sequencer)::get(null,"","seqr",seqr))
      `uvm_fatal(...)

    `uvm_do_on_with(apb_tr,seqr,{apb_tr.m_bvPaddr == addr; apb_tr.m_bvPdata == data});
    get_response(apb_tr);
  endtask
endclass