System Verilog随机和约束

随机数组和队列，约束动态数组和队列
示例1
my_trans.sv文件

class my_trans;
    rand bit [3:0]   s_array[7];//非合并数组
    rand bit [3:0]   d_array[ ];//动态数组，使用rand修饰，每次随机化这个类，这个变量都会赋一个值
    rand bit [3:0]   queue[$];//队列，$代表最后一个元素

    constraint  d_array_cons {d_array.size() > 5; d_array.size() < 10; }//size()内建方法返回数组的当前尺寸
    constraint  queue_cons {queue.size()==3;}//size()返回队列中元素的数目，队列为空返回为0；
    function void display();
        $display("s_array = %p", s_array);//%p各式符输出指针指向的地址值
	foreach (d_array[i])
	    $display("d_array[d_array[%0d] = 0x%0h", i, d_array[i]);
        $display("queue = %p", queue);
    endfunction
endclass

tb.sv文件

module tb;
my_trans trans;//例化
initial begin
    trans = new();//分配空间，产生一个包
    trans.randomize();//调用randomize函数，让rand修饰符起作用随机，并调用约束
    trans.display();
end
endmodule

Makefile文件

TB_FILE_LIST  =  filelist.list

all: clean comp run

COMP = vcs -full64 -sverilog -debug_all -fsdb

SIMV = ./simv

comp:
	$(COMP) -f $(TB_FILE_LIST) 
run:
	$(SIMV) -l simv.log
clean:
	rm -rf AN.DB DVEfiles csrc *.simv *.simv.daidir ucli.key 64
	rm -rf *.log* *.vpd *.fsdb *.vdb novas* *verdi*
	rm -rf simv*

filelist文件

./my_trans.sv
./tb.sv

执行make comp和make run命令

s_array = '{'h9, 'hc, 'h7, 'h3, 'hc, 'h4, 'h9} 
d_array[d_array[0] = 0x3
d_array[d_array[1] = 0x4
d_array[d_array[2] = 0x6
d_array[d_array[3] = 0x2
d_array[d_array[4] = 0x9
d_array[d_array[5] = 0xb
queue = '{'h6, 'h9, 'ha} 

示例2
my_trans.sv文件

class my_trans;
  rand  bit    [7:0]      sa;
  randc bit    [7:0]      da;		//port selection
        reg    [7:0]      payload[$];	// data array
        string            name;		// unique identifier
        int               low, high;

  function new(string name = "Packet");
      this.name = name;
      this.sa   = sa;
      this.da   = da; 
  endfunction

  constraint addr_cons { sa inside {[0:99]};
                         da inside {[100:200]};
			}
  function void display(string prefix = "NOTE");
      $display("[%s]%t %s sa = %0d, da = %0d", prefix, $realtime, name, sa, da);
      foreach(payload[i])
        $display("[%s]%t %s payload[%0d] = %0d", prefix, $realtime, name, i, payload[i]);
  endfunction
endclass

tb.sv文件

module tb_top;
    my_trans pkt0, pkt1, pkt2;
    initial begin
        pkt0 = new();
        pkt0.sa =1;
    	pkt0.da =2;
	    pkt0.display();

        pkt1 = new ();
        pkt1.sa = $urandom();//二次随机约束覆盖前面的随机约束
	    pkt1.da = $urandom();
	    pkt1.display();

	    pkt2 = new ();
        for(int i=0; i<5; i++) begin
            assert (pkt2.randomize ());//调用了rand，randc和constraint，使用断言检查randomize ()的结果，如果随机化成功，函数返回1，随机化失败，函数返回0
	    pkt2.display();
	    end
    end

    my_trans pkt[5];//例化5个pkt，pkt0, pkt1, pkt2，pkt3, pkt4
    initial begin
        for(int i =0 ; i< $size(pkt); i++) begin
            pkt[i] = new();
	        pkt[i].sa = i;
	        pkt[i].da = i*i;
            pkt[i].display();
    	end
    end   
endmodule

执行make comp和make run命令

[NOTE]                   0 Packet sa = 1, da = 2
[NOTE]                   0 Packet sa = 125, da = 226
[NOTE]                   0 Packet sa = 46, da = 187
[NOTE]                   0 Packet sa = 65, da = 140
[NOTE]                   0 Packet sa = 13, da = 159
[NOTE]                   0 Packet sa = 76, da = 196
[NOTE]                   0 Packet sa = 5, da = 172
[NOTE]                   0 Packet sa = 0, da = 0
[NOTE]                   0 Packet sa = 1, da = 1
[NOTE]                   0 Packet sa = 2, da = 4
[NOTE]                   0 Packet sa = 3, da = 9
[NOTE]                   0 Packet sa = 4, da = 16

rand与randc区别：rand相当于掷骰子，1-6的概率每次都一样，而randc必须经过一个周期随机之后才会出重复，第一轮肯定不会一样。