vcs用不同define例化相同module的说明

现有一个文件aaa.v
module aaa(
clk,
in,

    out

);

input clk;
input in;

output [1:0] out;

wire [1:0] out;

`ifdef PATH1

assign out = 2’b0;

`elsif PATH2

assign out = 2’b1;

`else

assign out = 2’b11;

`endif

endmodule

有一个文件top_a.v
module top_a(
clk,
in,

out
);

input clk;
input in;

output [1:0] out;

wire [1:0] out;

aaa u_aaa(
.clk (clk),
.in (in),
.out (out)
);

endmodule

有一个文件top_b.v
module top_b(
clk,
in,

out
);

input clk;
input in;

output [1:0] out;

wire [1:0] out;

aaa u_aaa(
.clk (clk),
.in (in),
.out (out)
);

endmodule

做2个define的vh文件
top_a.vh
`define PATH1

top_b.vh
`ifdef PATH1

`undef PATH1

`endif

`define PATH2

新建一个文件夹tmp，将aaa.v copy到tmp，做2个lst文件
1.lst
./top_a.vh
./top_a.v
./aaa.v

2.lst
./top_b.vh
./top_b.v
./tmp/aaa.v

新建文件synopsys_sim.setup
WORK > DEFAULT
DEFAULT : ./work
L1 : ./lib1
L2 : ./lib2
L3 : ./lib3

新建文件cfg.v
config topcfg;

design L3.top

endmodule

新建文件top.v
module top.v

wire clk;
wire in;

top_a u_top_a(
.clk (clk),
.in (in),

  .out  ()

)

top_b u_top_b(
.clk (clk),
.in (in),

  .out  ()

)

initial begin
#1;
$vcdpluson(0,top);
end

initial begin

#5000;
$finish();
end

endmodule

输入编译指令
vlogan –full64 +v2k –f 1.lst –work L1
vlogan –full64 +v2k –f 2.lst –work L2
vlogan –full64 +v2k top.v –work L3
vlogan –full64 +v2k cfg.v
vcs –full64 work.topcfg –liblist L1+L2+L3 –diag libconfig –libmap_verbose –debug_access+all

输入仿真指令
./simv

会得到vpd波形文件