Programming the Programmable Logic

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841833/Programming+the+Programmable+Logic

Programming the Programmable Logic

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Last modified Oct 11, 2018 by navam

Table of Contents

Note: xilinx_devcfg.c driver got deprecated in 2018.1 release. Use ZYNQ FPGA manager to program Bitstream into Zynq PL

Introduction

HW IP Features

Known Issues and Limitations

Kernel Configuration Options for Driver

Devicetree

Task Dependencies (Pre-requisites)

Tools Required

Input Files Required

Test procedure

Programming ZYNQ PL through Linux

Programming the PL through the FSBL

Programming the PL through U-Boot

Change Log

2016.3

Related Links

Solution Zynq7000 PL Programming
 

Note: xilinx_devcfg.c driver got deprecated in 2018.1 release. Use ZYNQ FPGA manager to program Bitstream into Zynq PL

 

Introduction

The Zynq Programmable Logic (PL) can be programmed by the First Stage Bootloader (FSBL), U-Boot or through Linux. Programming the PL at different stages may be advantageous for different projects and workflows.
 

HW IP Features

• Full Bitstream and partial Bitstream loading.
• Encrypted and Authenticated Bitstream loading.

 

Known Issues and Limitations

• Not support Partial,Encrypted,Authenticated Bitstream programming.

 

Kernel Configuration Options for Driver

Device Drivers ---> Character devices ---> <*> Xilinx Device Configuration

 

Devicetree

devcfg: devcfg@f8007000 {                         compatible = "xlnx,zynq-devcfg-1.0";                         interrupt-parent = <&&intc>;                         interrupts = <0 8 4>;                         reg = <0xf8007000 0x100>;                         clocks = <&&clkc 12>, <&&clkc 15>, <&&clkc 16>, <&&clkc 17>, <&&clkc 18>;                         clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";                         syscon = <&&slcr>;                 };

Task Dependencies (Pre-requisites)

• Setup Xilinx tools and environment

 

Tools Required

• Xilinx SDK

 

Input Files Required

• fsbl.elf
• bitstream.bit
• If using U-Boot
  • u-boot.elf
• If using Linux
  • uImage
  • uramdisk.tar.gz
  • devicetree.dtb

 

Test procedure

Programming ZYNQ PL through Linux

Once booted into Linux, write the bitstream file to the devcfg device:

$ cat bitstream.bit > /dev/xdevcfg

After, the prog_done file should indicate that the programming was successful.

$ cat /sys/class/xdevcfg/xdevcfg/device/prog_done 1

Programming the PL through the FSBL

The First Stage Boot-Loader (FSBL) is capable of programming the PL before loading U-Boot, which may be necessary for some applications. To have the FSBL load the PL, include the bitstream file when generating boot.bin and boot normally.
References:

• Prepare Boot Image
• Prepare Boot Medium

 

Programming the PL through U-Boot

Load the bitstream into memory and then use fpga loadb to program the PL; for example:

U-Boot> fatload mmc 0 0x4000000 bitstream.bit U-Boot> fpga loadb 0 0x4000000 <bitstream file size>

Change Log

2016.3

• char: devcfg: Add bitstream version check.

Related Links

Getting Started
U-Boot
New Horizons Zynq Blog
Partial Reconfiguration Documentation

Platform Specific Documentation
Zynq