VHDL-AMS 常用程序模块

VHDL-AMS 是硬件描述语言VHDL（IEEE 1076-1993）的一个衍生部分。它包含了模拟和混合信号的扩展，从而能够对模拟和混合信号系统的行为进行描述。

基础模块

```
--------------------------------
--  电阻
---------------------------------

LIBRARY IEEE;
USE IEEE.electrical_systems.all;

ENTITY resist IS

    GENERIC( R_value : real := 1000.0);
    PORT (TERMINAL tp,tm : electrical);
END;

ARCHITECTURE equ OF resist IS

    QUANTITY v ACROSS i THROUGH tp TO tm;
BEGIN
    v == R_value*i;
END;
--------------------------------
--  电容
---------------------------------

LIBRARY IEEE;
USE IEEE.electrical_systems.all;

ENTITY condensateur IS

    GENERIC( C_value : real := 1.0e-6);
    PORT (TERMINAL tp,tm : electrical);
END;

ARCHITECTURE equ OF condensateur IS

    QUANTITY v ACROSS i THROUGH tp TO tm;
BEGIN
    i == C_value*v'dot;
--  C_value*v == i'integ;
END;
--------------------------------
--  直流电源 DC
---------------------------------

LIBRARY IEEE;
USE IEEE.electrical_systems.all;

ENTITY V_dc IS

    GENERIC( DC_value : real := 10.0);
    PORT (TERMINAL tp,tm : electrical);
END;

ARCHITECTURE equ OF V_dc IS

    QUANTITY v ACROSS i THROUGH tp TO tm;  
BEGIN
    v == DC_value;
END;
--------------------------------
--  交流电源 AC
---------------------------------

LIBRARY IEEE;
USE IEEE.electrical_systems.all;
USE IEEE.math_real.all;

ENTITY V_ac IS

    GENERIC( Vampl : real := 10.0;freq : real := 1.0e3; phase : real := 0.0);
    PORT (TERMINAL tp,tm : electrical);
END;

ARCHITECTURE equ OF V_ac IS

    QUANTITY v ACROSS i THROUGH tp TO tm;  
BEGIN
    v == Vampl*cos(math_2_pi*freq*NOW+phase);
END;
-------------------------------------------------
-- testbench
-------------------------------------------------
--LIBRARY IEEE;
--USE IEEE.electrical_systems.all;
--USE work.all;

--ENTITY test IS
--END;

--ARCHITECTURE equ OF test IS
--  TERMINAL ta,tb,tc : electrical;
--BEGIN
--  
--  VCC : ENTITY V_dc(equ) GENERIC MAP (5.0) PORT MAP (ta, electrical_ref);
--  Ve  : ENTITY V_ac(equ) GENERIC MAP (1.0) PORT MAP (ta, tb);
--  R1  : ENTITY resist(equ)  PORT MAP (tb, tc);
--  C1  : ENTITY condensateur(equ) GENERIC MAP (1.0E-6) PORT MAP (tc, electrical_ref);
--END;

--------------------------------
--  例子 ：限制器
---------------------------------

LIBRARY IEEE;
USE IEEE.electrical_systems.all;

ENTITY limiteur IS

    GENERIC( limp : real := 15.0;limm : real := 15.0);
    PORT (TERMINAL te,ts : electrical);
END;

ARCHITECTURE behav  OF limiteur IS

    QUANTITY ve ACROSS  te TO electrical_ref;
    QUANTITY vs ACROSS  io THROUGH ts ;
BEGIN
    IF ve>limp USE
        vs == limp;
    ELSIF ve<-limm USE
        vs == -limm;
    ELSE
        vs == ve;
    END USE;

END;
-------------------------------------
--  比较器
-------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;

ENTITY comparator IS

GENERIC( seuil : real := 2.5);
PORT (TERMINAL tp,ref : electrical;SIGNAL dout : OUT boolean);
END;

ARCHITECTURE ideal  OF comparator IS

QUANTITY vin ACROSS  tp TO ref;

BEGIN
dout<=vin'above(seuil);

END;
-------------------------------------
--  简单的比较器
-------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;

ENTITY comparateur IS

GENERIC( level : real := 2.5);
PORT (TERMINAL ta : electrical;SIGNAL sd : OUT bit);
END;

ARCHITECTURE simple  OF comparateur IS

QUANTITY vin ACROSS  ta ;

BEGIN
PROCESS (vin'above(level))
BEGIN
IF vin'above(level) THEN
sd<='1';
ELSE
sd<='0';
END IF;
END PROCESS;
END;

ARCHITECTURE simple2  OF comparateur IS

QUANTITY vin ACROSS  ta ;

BEGIN
sd<='1' WHEN vin'above(level)ELSE '0';
END;
----------------------------------
--   test bench
----------------------------------
--LIBRARY IEEE;
--USE IEEE.electrical_systems.all;
--USE work.all;

--ENTITY test IS 
--END;

--ARCHITECTURE equ OF test IS
--TERMINAL ta  : electrical; 
--SIGNAL sd : bit ;
--BEGIN

--Ve  : ENTITY V_ac(equ) GENERIC MAP (5.0,1000.0) PORT MAP (ta, electrical_ref);
--vcomp : ENTITY comparateur  PORT MAP (ta,sd);
--
--END;
------------------------------------------------
-- 脉冲发生器
------------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;

ENTITY pulse_gen IS
GENERIC ( plow   : real := 0.0;
phigh  : real := 5.0;
trise  : real := 1.0e-6;
tfall  : real := 1.0e-6;
idelay : time := 1 ms;
pwidth : time := 5 ms) ;

PORT (TERMINAL t : electrical);
END;

ARCHITECTURE bhv OF pulse_gen IS
QUANTITY vout ACROSS iout THROUGH t;
SIGNAL spulse : real := PLOW;
BEGIN
PROCESS BEGIN
WAIT FOR idelay;
LOOP 
spulse <= PHIGH;
WAIT FOR PWIDTH;
spulse <= PLOW;
WAIT FOR PWIDTH;
END LOOP;
END PROCESS;
vout == spulse;
BREAK ON spulse;
END;
ARCHITECTURE bhv2 OF pulse_gen IS
QUANTITY vout ACROSS iout THROUGH t;
SIGNAL spulse : real := PLOW;
BEGIN
PROCESS BEGIN
WAIT FOR idelay;
LOOP 
spulse <= PHIGH;
WAIT FOR PWIDTH;
spulse <= PLOW;
WAIT FOR PWIDTH;
END LOOP;
END PROCESS;
vout == spulse'ramp(trise,tfall);

END;

-------------------------------------------
--  有初始化的电容器
-------------------------------------------

LIBRARY IEEE;
USE IEEE.electrical_systems.all;

ENTITY capacitor IS

GENERIC( C_value : real := 1.0e-6;V0 : real := real'low);
PORT (TERMINAL tp,tm : electrical);
END;

ARCHITECTURE equ OF capacitor IS

QUANTITY v ACROSS i THROUGH tp TO tm;
BEGIN
i == C_value*v'dot;
BREAK v=>V0 WHEN V0/=real'low;
--  C_value*v == i'integ;
END;

ARCHITECTURE equ2 OF capacitor IS

QUANTITY v ACROSS i THROUGH tp TO tm;
QUANTITY q : charge;
BEGIN
q == C_value*v;
i == q'dot;
BREAK FOR q USE v=>V0 WHEN V0/=real'low;
--  C_value*v == i'integ;
END;
----------------------------------------------
--  双初始条件电容
----------------------------------------------

LIBRARY IEEE;
USE IEEE.electrical_systems.all;

ENTITY capacitor2 IS

GENERIC( C_value : real := 1.0e-6; V0 : real := real'low);
PORT (TERMINAL tp,tm : electrical);
END;

ARCHITECTURE equ OF capacitor2 IS

QUANTITY v ACROSS i THROUGH tp TO tm;
BEGIN
IF DOMAIN = QUIESCENT_DOMAIN USE
v==V0;
ELSE
i == C_value*v'dot;
END USE;

END;

--------------------------------
--  交流电源 AC
---------------------------------

LIBRARY IEEE;
USE IEEE.electrical_systems.all;
USE IEEE.math_real.all;

ENTITY V_ac IS

GENERIC( Vampl : real := 10.0;freq : real := 1.0e3; phase : real := 0.0);
PORT (TERMINAL tp,tm : electrical);
END;

ARCHITECTURE equ OF V_ac IS
CONSTANT ac_mag : real := 1.0;
CONSTANT ac_phase : real := 0.0;
QUANTITY ac_spec : real SPECTRUM ac_mag, ac_phase;
QUANTITY v ACROSS i THROUGH tp TO tm;  
BEGIN
IF DOMAIN = FREQUENCY_DOMAIN USE
v == ac_spec;
ELSE
v == Vampl*cos(math_2_pi*freq*NOW+phase);
END USE;
END;

ARCHITECTURE equ2 OF V_ac IS
CONSTANT ac_mag : real := 1.0;
CONSTANT ac_phase : real := 0.0;
QUANTITY ac_spec : real SPECTRUM ac_mag, ac_phase;
QUANTITY v ACROSS i THROUGH tp TO tm;  

BEGIN
v == Vampl*cos(math_2_pi*freq*NOW+phase)+ac_spec;
END;

------------------------------------------------
--    test bench (带通)
------------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
USE work.all;

ENTITY test IS 
END;

ARCHITECTURE equ OF test IS
   TERMINAL tb, tc : electrical;
BEGIN
   VAC : ENTITY V_ac  PORT MAP (tb, electrical_ref);
  R1 : ENTITY Resist(equ)  PORT MAP (tb, tc);
RLC1 : ENTITY RLCp GENERIC MAP (1.0e3,25.0e-3,1.0e-6) PORT MAP (tc, electrical_ref);
end;

-------------------------------------------
--有热噪声性质的电阻
-------------------------------------------
--amb_temp est une variable partag閑
--{library clause}
LIBRARY IEEE;
USE IEEE.electrical_systems.ALL;

ENTITY R_noise IS
GENERIC (R_value : real := 1000.0);
PORT (TERMINAL vp, vm : electrical);
END;
ARCHITECTURE equ OF R_noise IS
QUANTITY V ACROSS I THROUGH vp TO vm;
CONSTANT amb_temp : real := 300.0;
CONSTANT K : real := 1.0;
   QUANTITY noise_src : real NOISE 4.0*amb_temp*K/R_value;
BEGIN
         V==R_value*I+noise_src;
END;
----------------------------------------------
-- RC 滤波
----------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;

ENTITY filtreRC_pb IS

GENERIC (Rv : real := 1.0e3; Cv : real := 1.0e-6);
PORT (TERMINAL tin, tout : electrical);
END;

ARCHITECTURE simple OF filtreRC_pb IS
QUANTITY vin ACROSS iin THROUGH tin;
QUANTITY vout ACROSS iout THROUGH tout;
BEGIN
vin-vout==Rv*Cv*vout'dot;
iin == 0.0;
END;

ARCHITECTURE laplace OF filtreRC_pb IS
QUANTITY vin ACROSS iin THROUGH tin;
QUANTITY vout ACROSS iout THROUGH tout;
CONSTANT num : real_vector := (1.0,0.0);
CONSTANT den : real_vector := (1.0, Rv*Cv);
BEGIN
vout==vin'ltf(num,den);
iin == 0.0;
END;
----------------------------------------
--  test bench RC 滤波
----------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
USE work.all;

ENTITY test IS END;

ARCHITECTURE equ OF test IS
TERMINAL te,ts : electrical;
BEGIN
VAC : ENTITY V_AC PORT MAP (te, electrical_ref);
filtre : ENTITY filtreRC_pb(laplace) PORT MAP (te,ts);
END;
--------------------------------
-- 二极管
--------------------------------
LIBRARY IEEE;
USE ieee.electrical_systems.all;
USE ieee.fundamental_constants.all;
USE Ieee.math_real.all;

ENTITY diode IS
GENERIC (Iss : real := 1.0e-14; n : real := 1.0; vj : real := 0.8;tt, cj0,rs : real :=0.0;
temperature : real := 300.0);
PORT (TERMINAL anode, cathode : electrical);
END;

ARCHITECTURE phys1 OF diode IS
QUANTITY vd ACROSS id,ic THROUGH anode TO cathode;
QUANTITY qc : charge;
CONSTANT vt : real := phys_k*temperature/PHYS_Q;
BEGIN
ic == qc'dot;
qc == tt*id-2.0*cj0*(vj**2-vj*vd)**0.5;
id == iss*(exp((vd-rs*id)/(n*vt))-1.0);
END;

ARCHITECTURE phys2 OF diode IS
TERMINAL ti : electrical;
QUANTITY vd ACROSS id,ic THROUGH ti TO cathode;
QUANTITY qc : charge;
CONSTANT vt : real := phys_k*temperature/PHYS_Q;
BEGIN
ri : entity work.resistance generic map (rs) port map (anode , ti);
ic == qc'dot;
qc == tt*id-2.0*cj0*(vj**2-vj*vd)**0.5;
id == iss*(exp(vd/(n*vt))-1.0);
END;

--ARCHITECTURE ideal OF diode IS
--CONSTANT VT0 : real := 0.65;
--CONSTANT ra : real := 10.0;
--QUANTITY vd ACROSS id THROUGH anode TO cathode;
--BEGIN
--IF vd<VT0 USE
--id == 0.0;
--ELSE
--vd == VT0+ra*id;
--END USE;
--END;
-------------------------------------------
--   有热噪声的二极管
-------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.ALL;
USE IEEE.thermal_systems.ALL;
USE IEEE.fundamental_constants.ALL;
USE ieee.math_real.ALL;

ENTITY diodth IS
GENERIC (Iss : real := 1.0e-12; n : real := 1.0; tt, cjo, vj, rs : real := 0.0) ;
PORT (TERMINAL anode , cathode : electrical; TERMINAL junction : thermal );
END;

ARCHITECTURE level0 OF diodth IS
QUANTITY vd ACROSS id,ic THROUGH anode TO cathode;
QUANTITY temp ACROSS power THROUGH junction  TO thermal_ref ;
QUANTITY qc : charge;
QUANTITY vt : voltage; -- electromagneticforce=tension
BEGIN
ic ==qc'dot;
qc ==tt*id-2.0*cjo*(vj**2-vj*vd)**0.5;
id == iss*(exp((vd-rs*id)/(n*vt))-1.0);
vt==temp*phys_K/phys_Q;
power==-vd*id;
END ARCHITECTURE level0;
----------------------------------------
-- 热敏电阻
----------------------------------------
LIBRARY IEEE;
USE IEEE.thermal_systems.ALL;

ENTITY Resistanceth IS
GENERIC (R_thermique : real := 100.0) ;
PORT (TERMINAL tpth,tmth : thermal );
END;

ARCHITECTURE level0 OF Resistanceth IS
QUANTITY temp ACROSS power THROUGH tpth TO tmth;

BEGIN
temp ==R_thermique*power;
END ARCHITECTURE level0;
----------------------------------------
-- 热敏电容
----------------------------------------
LIBRARY IEEE;
USE IEEE.thermal_systems.ALL;

ENTITY capath IS
GENERIC (C_thermique : real := 1.0e-3;T_amb : real :=300.0) ;
PORT (TERMINAL tpth,tmth : thermal );
END;

ARCHITECTURE level0 OF capath IS
QUANTITY temp ACROSS power THROUGH tpth TO tmth;

BEGIN
BREAK temp=>T_amb;
power ==C_thermique*temp'dot;
END ARCHITECTURE level0;
---------------------------------------
-- 热源
---------------------------------------
LIBRARY IEEE;
USE IEEE.thermal_systems.ALL;

ENTITY sourceth IS
GENERIC (C_thermique : real := 1.0e-3) ;
PORT (TERMINAL tpth,tmth : thermal );
END;

ARCHITECTURE level0 OF sourceth IS
QUANTITY temp ACROSS power THROUGH tpth TO tmth;
CONSTANT T_amb : real := 300.0;

BEGIN
power ==T_amb/100.0;
END ARCHITECTURE level0;
------------------------------------------
--   热测试
------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.ALL;
USE IEEE.thermal_systems.ALL;
USE work.ALL;

ENTITY test IS END;

ARCHITECTURE test_a OF test IS
TERMINAL anode  : electrical; 
TERMINAL junction : thermal;
BEGIN
VDD : ENTITY V_dc generic map (0.6) PORT MAP (anode,electrical_ref);
D1  : entity diodth port map (anode,electrical_ref,junction);
Rth1: ENTITY Resistanceth port map (junction, thermal_ref);
Cth1 : ENTITY Capath port map (junction, thermal_ref);
sth1 : ENTITY sourceth port map (thermal_ref,junction);
END;
------------------------------------------------
--  CTP热敏电阻
------------------------------------------------
library ieee;
use ieee.electrical_systems.all;

ENTITY CTP IS
GENERIC (R_value_zero_degre_C : real := 1000.0; R_coeff : real := 1.0);
PORT (TERMINAL tp,tm : electrical; QUANTITY temp : IN real);
END;

ARCHITECTURE simple Of CTP IS
QUANTITY V ACROSS I THROUGH tp TO tm;
BEGIN
V==R_value_zero_degre_C*(1.0+R_coeff*temp)*I;
END;

--------------------------------------------
-- 热源
--------------------------------------------
library ieee;
use ieee.electrical_systems.all;

ENTITY sourceT IS
PORT ( QUANTITY temp : OUT real);
END;

ARCHITECTURE simple Of sourceT IS

BEGIN
temp == now;
END;----------------------------------------------
---------------------------------------
-- NMOS
---------------------------------------
LIBRARY IEEE;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;
USE IEEE.MATH_REAL;

ENTITY NMOS IS
    GENERIC (Vt : REAL := 0.55; beta : real := 70.0e-6);
    PORT ( TERMINAL drain, gate, source, bulk : ELECTRICAL);
END ENTITY NMOS;
-- architecture
ARCHITECTURE a_NMOS OF NMOS IS
    CONSTANT RN : real := 1.0e9;
    QUANTITY VDS ACROSS IDS,IRN THROUGH drain TO source;
    QUANTITY VGS ACROSS gate TO source;
    QUANTITY Vbss ACROSS bulk TO source;
BEGIN
    IF VGS<Vt USE
        Ids==0.0;
    ELSE
        IF VDS<VGS-VT USE
            IDS==beta*((VGS-VT)*VDS-(VDS**2.0)/2.0);
        ELSE
            IDS==beta*((VGS-VT)**2.0)/2.0;
        END USE;
    END USE;
    VDS == RN*IRN;

END ARCHITECTURE a_NMOS;
---------------------------------------
-- PMOS
---------------------------------------
LIBRARY IEEE;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;
USE IEEE.MATH_REAL;

ENTITY PMOS IS
    GENERIC (Vt : REAL := -0.55; beta : real := 70.0e-6);
    PORT ( TERMINAL drain, gate, source, bulk : ELECTRICAL);
END ENTITY PMOS;
-- architecture
ARCHITECTURE a_PMOS OF PMOS IS
    CONSTANT RP : real := 1.0e9;
    QUANTITY VDS ACROSS IDS,IRP THROUGH drain TO source;
    QUANTITY VGS ACROSS gate TO source;
    QUANTITY Vbss ACROSS bulk TO source;
BEGIN

     IF VGS>VT USE
        Ids==0.0;
    ELSE
        IF VDS>(VGS-VT) USE
            IDS==-beta*((VGS-VT)*VDS-(VDS**2.0)/2.0);
        ELSE
            IDS==-beta*((VGS-VT)**2.0)/2.0;
        END USE;
    END USE;
    VDS == RP*IRP;
END ARCHITECTURE a_PMOS;
------------------------------------------------
--  rampe
------------------------------------------------
library ieee;
use ieee.electrical_systems.all;

entity V_rampe is
    generic (   Vmin : real :=0.0; 
                pente : real := 1.0) ; 
    port (terminal tp,tm : electrical);
end entity V_rampe;

architecture behav of V_rampe is
        quantity v  across i through tp to tm;
begin
    v==Vmin+pente*NOW;
end;

---------------------------------------
-- CMOS
---------------------------------------
LIBRARY IEEE;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;
USE IEEE.MATH_REAL;

ENTITY CMOS IS
    GENERIC (mtype: real := 1.0;Vt : REAL := 0.55; beta : real := 70.0e-6);
    PORT ( TERMINAL drain, gate, source, bulk : ELECTRICAL);
END ENTITY CMOS;

-- architecture

ARCHITECTURE a_CMOS OF CMOS IS
    CONSTANT RDS : real := 1.0e9;
    QUANTITY VDS ACROSS IDS,IRDS THROUGH drain TO source;
    QUANTITY VGS ACROSS gate TO source;
    QUANTITY Vbss ACROSS bulk TO source;
BEGIN
    IF mtype*VGS<mtype*Vt USE
        Ids==0.0;
    ELSE
        IF mtype*VDS<mtype*(VGS-VT) USE
            IDS==mtype*beta*((VGS-VT)*VDS-(VDS**2.0)/2.0);
        ELSE
            IDS==mtype*beta*((VGS-VT)**2.0)/2.0;
        END USE;
    END USE;
    VDS == RDS*IRDS;

END ARCHITECTURE a_CMOS;
------------------------------------------------------
--  NMOS 和 PMOS 特性
------------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
use work.all;

entity caracteristique_CMOS IS end;

ARCHITECTURE Test OF caracteristique_CMOS IS
    TERMINAL tdd, td,tgn,tgp : electrical;
BEGIN
    VGN  : entity V_dc GENERIC MAP (2.0) PORT MAP (tgn,electrical_ref);
 --     NMOS1 : entity NMOS  PORT MAP (tdd,tgn,electrical_ref,electrical_ref);
    NMOS1 : entity CMOS  PORT MAP (tdd,tgn,electrical_ref,electrical_ref);

    VGP  : entity V_dc GENERIC MAP (3.0) PORT MAP (tgp,electrical_ref); 
    VDD  : entity V_dc GENERIC MAP (5.0) PORT MAP (td,electrical_ref);
--  PMOS1 : entity PMOS  PORT MAP (tdd,tgp,td,td);
    PMOS1 : entity CMOS GENERIC MAP (-1.0,-0.55) PORT MAP (tdd,tgp,td,td);
    VDS  : entity V_rampe GENERIC MAP(0.0,1.0) PORT MAP (tdd,electrical_ref);
END ;

--------------------------------------------------
---- CMOS 反相器
--------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
use work.all;

entity inverseur_CMOS IS end;

ARCHITECTURE Test OF inverseur_CMOS IS
    TERMINAL tdd, te,ts : electrical;
BEGIN
    VDD  : entity V_dc GENERIC MAP (5.0) PORT MAP (tdd,electrical_ref);
--  PMOS1 : entity PMOS   PORT MAP (ts,te,tdd,tdd);
    PMOS1 : entity CMOS GENERIC MAP (-1.0,-0.55) PORT MAP (ts,te,tdd,tdd);

--  NMOS1 : entity NMOS   PORT MAP (ts,te,electrical_ref,electrical_ref);
    NMOS1 : entity CMOS   GENERIC MAP (1.0,0.55) PORT MAP (ts,te,electrical_ref,electrical_ref);

    VGG  : entity V_rampe GENERIC MAP(0.0,1.0) PORT MAP (te,electrical_ref);
END;
-----------------------------------------------------
--    静态/动态 MOS
-----------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;
use ieee.fundamental_constants.all;
----------------------------------
----------    ENTITIE   ----------
----------------------------------

entity mos is 
         generic( Vt0 : real := 0.85;----Volt
                  Weff: real :=0.8;----um
                  Leff: real :=0.55  ;----um
                  Kp : real := 120.0;----uA/V**2
                  gamma : real :=0.7;----V**0.5
                  ni : real :=1.45e-2;----um**-3
                  Nsub : real :=52.0e3;----um**-3
                  lam: real:=0.001; ----V**-1   
                  T : real := 300.0); ----K

           port ( terminal drain, gate, source, bulk : electrical);
end mos;

--------------------------------------------------
-------- ARCHITECTURE
--------------------------------------------------

architecture mos1 of mos is 

--------------------

   function draincourant(constant Vgs, Vds, Vbs :real ) return real is

            variable vt, phi, vth, vdsat, result :real;

      begin

                  Vt:=phys_K*T/phys_q;
                  Phi := 2.0*Vt*log( Nsub/ni);

                  if Vbs<=0.0 then 

                            vth := Vt0-gamma*sqrt(phi)+gamma*sqrt(Phi-Vbs);
                  else 
                            vth :=Vt0-gamma*0.5*Vbs/sqrt(phi);
                  end if;

                  vdsat :=vgs-vth;

                  if vgs < vth then
                           result:=0.0;
                  else if Vds < (Vgs -Vth) then

                        result := (Kp*Weff/Leff)*Vds*(Vgs-Vth-Vds/2.0)*(1.0+lam*vds);
                  else 
                         result :=((Kp*Weff)/(2.0*Leff))*((Vgs - Vth)**2.0)*(1.0+lam*vds);
                  end if;


                  end if;
      return result; 

   end function;
---    -----

          quantity Id through drain to source; 
          quantity Vbs across bulk to source; 
          quantity Vds across drain to source; 
          quantity Vgs across gate to source;
begin 


        Id == draincourant(Vgs, Vds, Vbs)*1.0e-6;

end architecture mos1;


---------------------------- 
----capacites du mos---
----------------------------


library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;
use ieee.fundamental_constants.all;
----------------------------------
----------    ENTITIE   ----------
----------------------------------

entity moscap is 
         generic( Vt0 : real := 0.85;
                  Weff: real :=0.8;
                  Leff: real :=0.55 ;
                  cox: real :=2.75e-15;
                  Kp : real := 120.0;
                  gamma : real :=0.7;
                  ni : real :=1.45e-2;
                  Nsub : real :=52.0e3;
                  lam: real:=0.001;     
                  T : real := 300.0); 

           port ( terminal drain1, gate1, source1, bulk1: electrical);
end moscap;

--------------------------------------------------
-------- ARCHITECTURE
--------------------------------------------------

architecture mos1 of moscap is 
-----------------
 function threshold(constant Vgs, Vds, Vbs, vt, phi:real ) return real is

            variable result :real;

      begin

                  if Vbs<=0.0 then 

                            result := Vt0-gamma*sqrt(phi)+gamma*sqrt(Phi-Vbs);
                   else 
                            result :=Vt0-gamma*0.5*Vbs/sqrt(phi);
                   end if;
                   return result;     

   end function;

          constant capox: real :=cox*weff*leff;
          constant Vt: real :=phys_K*T/phys_q;
          constant Phi: real:= 2.0*Vt*log( Nsub/ni);

          quantity vth:real;
          quantity vdsat:real;
          quantity Vbs across bulk1 to source1; 
          quantity Vds across drain1 to source1; 
          quantity Vdb across drain1 to bulk1;


          quantity Vgs across igs through gate1 to source1;
          quantity Vgd across igd through gate1 to drain1;
          quantity Vgb across igb through gate1 to bulk1;

          quantity Cgb:real;
          quantity Cgd:real;
          quantity Cgs:real;

begin 

        vth == threshold(vgs, Vds, Vbs, vt, phi);       
        vdsat==vgs-vth;

        if (vgs-vth)<=-phi use

              Cgb==capox;
              Cgd==0.0;
              Cgs==0.0;

        else if (vgs-vth)<=-phi/2.0 and (vgs-vth)>-phi use

              Cgb==-capox*(vgs-vth)/phi;
              Cgd==0.0;
              Cgs==0.0;

        else if (vgs-vth)<0.0  and (vgs-vth)>-phi/2.0  use

              Cgb==-capox*(vgs-vth)/phi;
              Cgd==0.0;
              Cgs==(capox/1.5)*(2.0*(vgs-vth)/phi+1.0);

        else              
                  if  vds<vdsat  use
                      Cgb==0.0;
                      Cgd==(capox/1.5)*(1.0-((vdsat-vbs)/(2.0*(vdsat-vbs)-vdb))**2.0);
                      Cgs==(capox/1.5)*(1.0-((vdsat-vds)/(2.0*(vdsat-vbs)-vdb))**2.0);      
                  else
                      Cgb==0.0;
                      Cgd==0.0;
                      Cgs==capox/1.5;
                  end use;
        end use;
        end use;
        end use;

        igs == Cgs * Vgs'dot; 
        igd == Cgd * Vgd'dot;
        igb == Cgb * Vgb'dot;


end architecture mos1;
---------------------------------
library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;
use ieee.fundamental_constants.all;

entity mos3 is

            port (terminal gg,dd,ss,bb: electrical);

end entity mos3;


architecture structural of mos3 is


begin

     tranmos: entity work.mos(mos1)
              port map ( gate=>gg ,drain=> dd, source=> ss,  bulk=>bb );

     capa: entity work.moscap(mos1)
              port map ( gate1=>gg , drain1=> dd, source1=> ss,  bulk1=>bb );

end architecture structural;
------------------------------------------------------
------------------------------------------------------
--  动态NMOS特性 
------------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
use work.all;

entity caracteristique_MOS IS end;

ARCHITECTURE Test OF caracteristique_MOS IS
    TERMINAL tdd, td,tgn,tgp : electrical;
BEGIN
    VGN  : entity V_dc GENERIC MAP (2.0) PORT MAP (tgn,electrical_ref);
    NMOS1 : entity MOS3  PORT MAP (tgn,tdd,electrical_ref,electrical_ref);
    VDS  : entity V_rampe GENERIC MAP(0.0,1.0) PORT MAP (tdd,electrical_ref);
END ;



----------------------------------------
-- 有package的模式
----------------------------------------
---------------------------------------
--   package mos_param
---------------------------------------
PACKAGE mos_param IS

CONSTANT    mtype : integer :=0; -- type de MOS (N=0 ou P=1)
CONSTANT    cw : real := 1.0e-4; -- largeur du canal
CONSTANT    cl : real := 1.0e-4; -- longueur du canal
CONSTANT    vt0 : real := 1.0;
CONSTANT    kp : real := 2.0e-5;
CONSTANT    gamma : real := 0.0;
CONSTANT    phi : real := 0.6;
CONSTANT    ld : real := 0.0;
CONSTANT    tox : real := 1.0e-7;
CONSTANT    u0 : real := 600.0 ;

END PACKAGE mos_param; 
----------------------------------------
-- MOS模式 .
----------------------------------------
library ieee;
use ieee.math_real.all;
use ieee.electrical_systems.all;
use ieee.fundamental_constants.all;
use work.mos_param.all;

entity MOS2 is
--  generic (   mtype : integer :=0; -- type de MOS (N=0 ou P=1)
--              cw : real := 1.0e-4;
--              cl : real := 1.0e-4; -- largeur/longueur du canal
--              vt0 : real := 1.0;
--              kp : real := 2.0e-5;
--              gamma : real := 0.0;
--              phi : real := 0.6;
--              ld : real := 0.0;
--              tox : real := 1.0e-7;
--              u0 : real := 600.0) ; 
    port (terminal drain, gate, source, bulk: electrical);
end entity MOS2;

architecture level0 of MOS2 is

    constant p: real := real(1 - 2*mtype); -- p = 1.0 pour NMOS, -1.0 pour PMOS
    constant EPS_SIO2 : real := 3.9*PHYS_EPS0;
    constant lambda : real := 0.01;
-- 计算漏极电流的值

function ids_dc ( vds, vbs, vgs  : real) return real is  

        variable cleff,vteff,betap, vgst,cox,kp2, result : real ;


begin
-- 模型参数的预处理
        cleff := cl - 2.0* ld;
    if tox <= 0.0       then 
        cox := EPS_SIO2*cw*cl/1.0e-7;
    else
         cox := EPS_SIO2*cw*cl/tox; 
    end if;
    if kp = 0.0 then kp2 := cox * u0; else kp2 := kp;end if;
    if vbs <= 0.0 then
        vteff := vt0 + gamma*(sqrt(phi-vbs)-sqrt(phi));
    else
        vteff := vt0 + gamma*(sqrt(phi+vbs)-sqrt(phi));
    end if;
    betap := kp2*cw/cleff;

------ 计算漏极电流
    vgst := vgs - vteff;
    if p*vgst <= 0.0 then
        result := (0.0); -- bloqu?
    elsif p*vgst <= vds then
        result := ( p*0.5 * betap * vgst**2)*(1.0+lambda*abs(vds)); -- 饱和
    else
        result := (p*betap * (p*vgst - 0.5*vds) *vds)*(1.0+lambda*abs(vds)); --线性模式
    end if;

        return result;
end function ids_dc;

    quantity vgs across gate to source;
    quantity vds across ids through drain to source;
    quantity vbs across bulk to source;
    quantity vgd across gate to drain;
    quantity vbd across bulk to drain;

begin

    ids == ids_dc(vds, vbs, vgs);

--      if p*vds >= 0.0 use
--      ids == ids_dc(vds, vbs, vgs); -- mode direct
--      else
--      ids == ids_dc(-vds, vbd, vgd);  -- mode inverse
--      end use;

end architecture level0;
------------------------------------------------------
--  有 package 的 NMOS 特性
------------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
use work.all;

entity caracteristique_MOS IS end;

ARCHITECTURE Test OF caracteristique_MOS IS
    TERMINAL tdd, td,tgn,tgp : electrical;
    CONSTANT cl : real :=1.0e-4;
BEGIN
    VGN  : entity V_dc GENERIC MAP (2.0) PORT MAP (tgn,electrical_ref);
    NMOS1 : entity MOS2   PORT MAP (tdd,tgn,electrical_ref,electrical_ref);
    VDS  : entity V_rampe GENERIC MAP(0.0,1.0) PORT MAP (tdd,electrical_ref);
END ;

--------------------------------
--加法放大器
--------------------------------

library ieee;
use ieee.electrical_systems.all;
package ELECTRICAL_BIS is
   -- type declarations
    CONSTANT a : real := 1.0;
   nature ELECTRICAL_VECTOR is array (NATURAL range <>) of ELECTRICAL;

end package ELECTRICAL_BIS;

library ieee;
use ieee.electrical_systems.all;
use electrical_bis.all;

entity weighted_summer is


    generic (beta, gamma: real_vector);
    port (  terminal inp, inm: electrical_vector; terminal o : electrical);
end entity weighted_summer;

architecture proc of weighted_summer is
    quantity vp across inp to electrical_ref;
    quantity vm across inm to electrical_ref;
    quantity vo across io through o to electrical_ref;
begin
    procedural is
        variable bvs, gvs: real := 0.0;
    begin
        for i in beta'range loop
            bvs := bvs + beta(i)*vp(i);
        end loop;
        for i in gamma'range loop
            gvs := gvs + gamma(i)*vm(i);
        end loop;
        vo := bvs - gvs;
    end procedural;
end architecture proc;

architecture simul of weighted_summer is
    quantity vp across inp;
    quantity vm across inm;
    quantity vo across io through o;

function "*" (a: real_vector; b: electrical_vector'across) return real is
    variable result: real := 0.0;
begin 
-- calcule le produit scalaire de a*b
    for i in a'range loop
        result := result + a(i)*b(i);
    end loop;
    return result;
end function "*";

begin
vo == beta*vp - gamma*vm;
end architecture simul;

----------------------------------------------------------
--分段线性电压源.
----------------------------------------------------------

package pwl_pkg is
    type pwl_tv is record
        t  : real;
        v : real;
    end record;
    type pwl_vector is array (natural range <>) of pwl_tv;
end package pwl_pkg;

library ieee;
use ieee.electrical_systems.all;
use work.pwl_pkg.all;

entity vpwl is
    generic (
        pwl_data: pwl_vector;
        trd: real := 1.0e-9 
            );
    port (terminal tp, tm: electrical);
end entity vpwl;

architecture bce of vpwl is
    alias data: pwl_vector(0 to pwl_data'length-1) is pwl_data;
    constant v0: real := data(0).v;
    quantity vout across iout through tp to tm;
    signal sdvdt: real := 0.0;
begin
    break vout => v0; -- condition initiale
    process
        begin
            sdvdt <= (data(1).v-data(0).v)/data(1).t;
            for i in 1 to data'right-1 loop
            sdvdt <= transport (data(i+1).v-data(i).v)/(data(i+1).t-data(i).t) after data(i).t*1 sec;
            end loop;
            wait;
    end process;
    vout'dot == sdvdt'ramp(trd);
end architecture bce;


---------------------------------------------------------------- 
-- 逐次逼近数模转换
----------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;

entity adc is
    generic (NBIT : natural := 8;
    VMIN : real := 0.0; -- 最小输入电压
    VMAX : real := 5.0; -- 最大输入电压
    DELAY: delay_length := 0 ns );-- 转换延迟
port ( terminal ain, ref: electrical; -- 模拟输入
    signal start : in std_logic; -- 转换开始
    signal clk : in std_logic; -- 时钟
    signal eoc : out std_logic; -- 转换结束
    signal dout : out std_logic_vector(NBIT-1 downto 0) ); -- mot de sortie
end entity adc;

architecture sa of adc is
    quantity uin across ain to ref; -- 输入电压读取
    signal uin_hold: real := 0.0; -- 采样的输入电压
begin
process
    variable delta : real := 0.0;
    variable vout : std_logic_vector(dout'range);
    variable bitidx : integer := dout'high;
    variable do_start: boolean := false;
begin
    wait on start, clk;
    if start'event and start = '1' then -- 新转换
        uin_hold <= uin - VMIN; -- 取样和标准化
        delta := VMAX - VMIN; -- 测试间隔
        bitidx := dout'high; -- 从MSB开始
        vout := (others => 'X');
        eoc <= '0';
        do_start := true;
    end if; -- start'event and start = '1'
    if clk'event and clk = '1' and do_start then -- 每个时钟转换1bit
        delta := delta/2.0;
        if uin_hold >= delta then
            vout(bitidx) := '1';
            uin_hold <= uin_hold - delta;
        else
            vout(bitidx) := '0';
        end if; -- uin_hold >= delta
        if bitidx = 0 then -- conversion termin閑
            eoc <= '1';
            do_start := false;
            dout <= vout after DELAY;
        else
            bitidx := bitidx - 1;
        end if; -- bitidx = 0
    end if; -- clk'event and clk = '1' and do_start
end process;
end architecture sa;
---------------------------
-- testbench 
---------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;

entity tb_adc_sa is end;

architecture bench of tb_adc_sa is
    constant NBIT : natural := 4; -- 比特数
    constant CLKP: time := 1 us; -- 时钟时长
    constant FSC : real := 5.0; -- 满刻度
    constant NMAX : integer := (NBIT+1)*(2**NBIT-1);
    constant TRF : time := NMAX*CLKP; -- dur閑 d'une rampe
    constant IDEL : time := 1 us; -- d閘ai initial du stimulus
    terminal tsrc: electrical;
    quantity usrc across isrc through tsrc;
    signal clk: std_logic := '0';
    signal done, start: std_logic;
    signal dout: std_logic_vector(NBIT-1 downto 0);
    signal ssrc: real := 0.0;

function time2real (tt: time) return real is
begin
    return  time'pos(tt)*1.0e-15; --(tt / 1 fs)*1.0e-15; --
end time2real;

begin
    UUT: entity work.adc(sa)
        generic map (
            NBIT => NBIT,
            VMIN => 0.0,
            VMAX => FSC,
            DELAY => 0 ns)
        port map (
            ain => tsrc,
            ref => electrical_ref,
            start => start,
            clk => clk,
            eoc => done,
            dout => dout);
    ssrc <= FSC after 1 ns, 0.0 after TRF;
    usrc == ssrc'ramp(time2real(TRF));
    clk_gen: clk <= not clk after CLKP/2;
    start_gen: process
        begin
            start <= '0';
            wait for IDEL;
            loop
                start <= '1';
                wait for NBIT*CLKP; -- attente de la fin d'une conversion
                start <= '0';
                wait for CLKP;
            end loop;
        end process start_gen;
end architecture bench;
----------------------------------------------------------
-- Mod鑜e comportemental g閚閞ique d'un CLA algorithmique.
----------------------------------------------------------
library ieee;
use ieee.electrical_systems.all;

entity dac is
    generic (
        N : natural := 8; -- r閟olution
        vref: real := 5.0); -- tension de r閒閞ence
port (
    signal rst, clk: in bit; -- reset, horloge
    signal din: in bit_vector(N-1 downto 0); -- mot a convertir
    signal done: out bit; -- fin de conversion
    terminal tout: electrical); -- sortie analogique
end entity dac;

architecture algo of dac is
    constant A0: real := vref/2.0; -- valeur LSB de r閒閞ence
    signal sout: real := 0.0;
    quantity uout across iout through tout;
begin
process (rst, clk)
    variable acc: real := 0.0;
    variable ib: natural := 0;
    variable vin: bit_vector(din'range);
    variable vdone: bit := '0';
begin
    if rst = '1' then -- reset asynchrone
        acc := 0.0;
        ib := 0;
        vin := din; -- 閏hantillonnage du mot d'entr閑
        vdone := '0';
elsif clk'event and clk = '1' then
    if vdone = '1' then
        ib := 0;
        acc := 0.0;
        vin := din; -- 閏hantillonnage du mot d'entr閑
        vdone := '0';
elsif ib <= vin'left - 1 then
    acc := acc/2.0 + real(bit'pos(vin(ib)));
    ib := ib + 1;
elsif ib = vin'left then -- bit de signe
    if vin(ib) = '1' then
        acc := -acc;
end if;
    acc := A0*acc;
    ib := ib + 1;
    sout <= acc; -- 閏hantillonnage en sortie
    vdone := '1';
end if;
end if; -- clk'event and clk = '1'
    done <= vdone;
end process;
    uout == sout'ramp(1.0e-9);
end architecture algo;
------------------------------------------------
--    testbench associ?
------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;
use work.all;

entity tb_dac_sa is end;

architecture bench of tb_dac_sa is
    CONSTANT    N : natural := 8; -- r閟olution
    CONSTANT    vref: real := 5.0; -- tension de r閒閞ence
    constant    CLKP: time := 1 us; -- p閞iode d'horloge
    constant    IDEL : time := 1 us; -- d閘ai initial du stimulus
    CONSTANT    CLKP1 : time := N*CLKP+CLKP;

    signal rst, clk:  bit :='0'; -- reset, horloge
    signal din:  bit_vector(N-1 downto 0):=(others=>'0'); -- mot a convertir
    signal done:  bit; -- fin de conversion
    terminal tout: electrical ; -- sortie analogique
--  quantity vout across iout through tout;

function time2real (tt: time) return real is
begin
    return  time'pos(tt)*1.0e-15; --(tt / 1 fs)*1.0e-15; --
end time2real;

begin
    UUT: entity work.dac
        generic map (N,vref)
        port map (
            rst, 
            clk,
            din, -- mot a convertir
            done, -- fin de conversion
             tout );
    rst <= '1' after 1 ns, '0' after IDEL;

    clk_gen: clk <= not clk after CLKP/2;
    din(0) <= not din(0) after CLKP1;
    din(1) <= not din(1) after (2*CLKP1);
    din(2) <= not din(2) after (4*CLKP1);
    din(3) <= not din(3) after (8*CLKP1);

end architecture bench;


--------------------------------------------
-- boucle ?verrouillage de phase 1
--------------------------------------------
-------------------------------------------
-- 模电VCO.
-------------------------------------------

library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;

entity vco1 is
    generic (
        Gvco: real := 100.0e3  -- gain du VCO [-]
            );
    port (terminal tin, tout,tm: electrical);
end entity vco1;
architecture beh of vco1 is
    quantity ve across tin TO tm;
    quantity v across i through tout TO tm;
begin
    v == sin(math_2_pi*(Gvco*ve+1.0e6)*now);
end architecture beh;
-----------------------------------------------
-- Le multiplieur
-----------------------------------------------

library ieee;
use ieee.electrical_systems.all;

entity mult is
    port (terminal tin1, tin2, tout,tm: electrical);
end entity mult;

architecture amult of mult is
    quantity uin1 across tin1 TO tm;
    quantity uin2 across tin2 TO tm;
    quantity uout across iout through tout TO tm;
begin
    uout == 2.5*uin1*uin2;
end architecture amult;

---------------------------------------------------------
-- Le filtre
---------------------------------------------------------

library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;

entity filtre is
    port (terminal tin, tout,tm: electrical);
end entity filtre;

architecture beh of filtre is
    constant zf: real := 20.0e3;
    constant num : real_vector (1 to 2) := (1.0, 0.0);
    constant den : real_vector (1 to 2) := (1.0, 1.0/(math_2_pi*zf));
    quantity uin across tin TO tm;
    quantity uout across iout through tout TO tm;
begin
    uout == uin'ltf(num,den);
end architecture beh;

-------------------------------------------
-- Le g閚閞ateur de test
-------------------------------------------

library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;

entity gene_sinus is
    generic (
        Ampl: real :=1.0;freq:real :=1.0e6;phase: real := 0.0  
            );
    port (terminal tp,tm: electrical);
end entity gene_sinus;

architecture beh of gene_sinus is
    quantity v across i through tp TO tm;
    quantity phasor : real SPECTRUM 1.0,0.0;
    constant w : real := math_2_pi*freq;    
begin
    v == Ampl*sin(w*now+phase)+phasor;
end architecture beh;

---------------------------------------------
-- Mod鑜e structurel de la PLL analogique.
---------------------------------------------

library ieee;
use ieee.electrical_systems.all;
use work.all;

entity pll1 is
end entity pll1;

architecture str of pll1 is
    terminal trf,tif,tctrl,tlo: electrical;
begin
    V1: entity gene_sinus
        generic map (1.0,10.0e5,0.0 )
        port map ( trf, electrical_ref  );
    M: entity mult
            port map (trf, trf,tif,electrical_ref);
    U: entity filtre
            port map (tif, tctrl,electrical_ref);
    VC: entity vco1
            generic map (100.0e3    )
            port map (tctrl,tlo,electrical_ref);
end architecture str;


-----------
-- PLL2 :
-----------

--------------------------------------------
--Mod鑜e du comparateur de phase analogique.
--------------------------------------------
library ieee;
use ieee.electrical_systems.all;

entity phcomp is
    generic (KPC: real := 1.0); -- gain [V/rad]
    port (terminal tin1, tin2, tout: electrical);
end entity phcomp;

architecture amult of phcomp is
    quantity uin1 across tin1;
    quantity uin2 across tin2;
    quantity uout across iout through tout;
begin
    uout == KPC*uin1*uin2;
end architecture amult;

-----------------------------------------------------
--Mod鑜e comportemental du filtre de boucle de type 1.
-----------------------------------------------------

library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;

entity lp1 is
    generic (   H0: real := 1.0; -- gain du filtre
            FP: real := 1.0e3); -- fr閝uence de coupure
    port (terminal inp, outp: electrical);
end entity lp1;

architecture ode of lp1 is
    constant WP: real := MATH_2_PI*FP;
    quantity uin across inp;
    quantity uout across iout through outp;
begin
    uout'dot + WP*uout == H0*WP*uin;
end architecture ode;

-------------------------------------------
--Mod鑜e comportemental du VCO analogique.
-------------------------------------------

library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;

entity vco is
    generic (
        GAIN : real := 1.0; -- gain du VCO [-]
        KVCO: real := 1.0; -- pente (sensibilit? du VCO [Hz/V]
        FC : real := 1.0e3; -- fr閝uence centrale [Hz]
        UC0 : real := 0.0 -- tension de commande ?f=FC [V]
        );
    port (terminal tin, tout: electrical);
end entity vco;

architecture ideal of vco is
    constant WC : real := MATH_2_PI*FC;
    constant KVCOR: real := MATH_2_PI*KVCO; -- [rad/(s*V)]
    quantity uin across tin;
    quantity uout across iout through tout;
    quantity dphiv, phiv: real; -- phase
begin
    dphiv == WC + KVCOR*(uin - UC0);
    phiv == dphiv'integ;
    uout == GAIN*sin(phiv);
end architecture ideal;

----------------------------------------
--Mod鑜e structurel de la PLL analogique.
----------------------------------------

library ieee;
use ieee.electrical_systems.all;

entity pll is
    generic (
        KPC : real := 1.0; -- gain du comparateur de phase [V/rad]
        HLF : real := 1.0; -- gain du filtre [-]
        FLF : real := 1.0e2; -- fr閝uence de coupure du filtre [Hz]
        KVCO: real := 1.0; -- sensibilit?du VCO [Hz/V]
        FC : real := 1.0e3; -- fr閝uence centrale du VCO [Hz]
        UC0 : real := 0.0 -- tension de commande du VCO ?f=FC [V]
    );
    port (terminal tref, tlf, tvco: electrical);
end entity pll;

architecture str of pll is
    terminal tpc: electrical;
begin
    I_PC: entity work.phcomp(amult)
        generic map (
            KPC => KPC
                    )
        port map (
            tin1 => tref,
            tin2 => tvco,
            tout => tpc
                );
    I_LF: entity work.lp1(ode)
        generic map (
            H0 => HLF,
            FP => FLF
                )
        port map (tpc, tlf);
    I_VCO: entity work.vco(ideal)
        generic map (
            KVCO => KVCO,
            FC => FC,
            UC0 => UC0
                )
        port map (tlf, tvco);
end architecture str;
---------------------------------------
--    test pll2
---------------------------------------
library ieee;
use ieee.electrical_systems.all;
use work.all;

entity pll2 is
end entity pll2;

architecture str of pll1 is
    terminal trf,tlf,tvco: electrical;
begin
    V1: entity gene_sinus
        generic map (1.0,1.0e3,0.0  )
        port map ( trf, electrical_ref  );
    P: entity pll
            port map (trf, tlf,tvco);

end architecture str;

------------------------------------------------
--4bits 加法器例子:
------------------------------------------------

ENTITY adder IS
    PORT (a,b,cin: IN bit; sum, cout : OUT bit);
END adder;

ARCHITECTURE rtl OF adder IS
BEGIN
    Sum<=(a xor b) xor cin;
    Cout<=(a and b) or (cin and a) or (cin and b);
END rtl ;

------------------------------------
--Description structurelle g閚閞ique
------------------------------------
library ieee;
use ieee.std_logic_1164.all;

ENTITY adder4 IS
    PORT (  a,b: IN bit_vector (4  DOWNTO 1);
                        cin: IN bit;
                        sum: OUT bit_vector (4  DOWNTO 1);
                        cout : OUT bit);
END adder4;

ARCHITECTURE structural OF adder4 IS
     COMPONENT compo1
         PORT(x, y, z : IN bit; v, t : OUT bit);
     END COMPONENT;
     SIGNAL carry : bit_vector(0 TO 4);
BEGIN
    carry(0)<=cin;
    add1: compo1 PORT MAP(a(1),b(1),carry(0),sum(1),carry(1));
    add2: compo1 PORT MAP(a(2),b(2),carry(1),sum(2),carry(2));
    add3: compo1 PORT MAP(a(3),b(3),carry(2),sum(3),carry(3));
    add4: compo1 PORT MAP(a(4),b(4),carry(3),sum(4),carry(4));
    cout<=carry(4);
END structural;

-----------------
--Configuration:
-----------------
use work.all;
CONFIGURATION test_adder4 OF adder4 IS
    FOR structural
        FOR ALL : compo1
        USE ENTITY WORK.adder(rtl)
 ;--         PORT MAP (a=>x, b=>y, cin=>z, sum=>v, cout=>t);
        END FOR;
   END FOR;
END CONFIGURATION test_adder4;

--------------------------------------------
--configuration incluse dans l'architecture
--------------------------------------------
ARCHITECTURE structural2 OF adder4  IS

COMPONENT compo1
        PORT(x, y, z : IN bit; v, t : OUT bit);
    END COMPONENT;
    SIGNAL carry : bit_vector(0 TO 4);

FOR ALL : compo1 USE ENTITY WORK.adder(rtl)
--      PORT MAP (a=>x, b=>y, cin=>z, sum=>v, cout=>t);
;-- END FOR;
BEGIN
    carry(0)<=cin;  
add1: compo1 PORT MAP(a(1),b(1),carry(0),sum(1),carry(1));
add2: compo1 PORT MAP(a(2),b(2),carry(1),sum(2),carry(2));
add3: compo1 PORT MAP(a(3),b(3),carry(2),sum(3),carry(3));
add4: compo1 PORT MAP(a(4),b(4),carry(3),sum(4),carry(4));
cout<=carry(4);
END structural2;

-------------------------------------------------------
-- 1 bit 加法器结构
-------------------------------------------------------

ENTITY add1 IS
    PORT (a,b,cin: IN bit; s, cout : OUT bit);
END add1;

architecture str of add1 is
-- 声明composants
    component c_or2 is
        port (z: out bit; i1, i2: in bit);
    end component c_or2;
    component c_and2 is
        port (z: out bit; i1, i2: in bit);
    end component c_and2;
    component c_xor2 is
        port (z: out bit; i1, i2: in bit);
    end component c_xor2;
signal s1, s2, s3, s4: bit; -- signaux locaux
begin
-- instances de composants
and1: c_and2 port map (i1 => a, i2 => b, z => s4);
and2: c_and2 port map (i1 => s2, i2 => cin, z => s3);
or1  : c_or2    port map (i1 => a, i2 => b, z => s2);
or2  : c_or2    port map (i1 => s3, i2 => s4, z => cout);
xor1 : c_xor2  port map (i1 => a, i2 => b, z => s1);
xor2: c_xor2   port map (i1 => s1, i2 => cin, z => s);
end architecture str;


--library CMOS;
configuration cfg_add1_str of add1 is
    for str -- pour l'architecture str
        for all: c_or2 -- pour toutes les instances c_or2
            use entity work.cmos_or2(timing)
;--         port map (i1 => a, i2 => b, o => s);
        end for; -- all: c_or2
        for all: c_and2 -- pour toutes les instances c_and2
            use entity work.cmos_and2(timing)
;--         port map (i1 => a, i2 => b, o => s);
        end for; -- all: c_and2
        for all: c_xor -- pour toutes les instances c_xor2
            use entity work.cmos_xor2(timing)
;--         port map (i1 => a, i2 => b, o => s);
        end for; -- all: c_xor2
    end for; -- str
end configuration cfg_add1_str;

--library CMOS;
architecture str2 of add1 is
    signal s1, s2, s3, s4: bit; -- signaux locaux
begin
-- instances de composants
and1: entity work.cmos_and2(timing) 
;--     port map (i1 => a, i2 => b, o => s4);
and2: entity work.cmos_and2(timing) 
;--     port map (i1 => s2, i2 => cin, o => s3);
or1 : entity work.cmos_or2(timing) 
;--     port map (i1 => a, i2 => b, o => s2);
or2 : entity work.cmos_or2(timing) 
;--     port map (i1 => s3, i2 => s4, o => cout);
xor1: entity work.cmos_xor2(timing) 
;--     port map (i1 => a, i2 => b, o => s1);
xor2: entity work.cmos_xor2(timing)
;--     port map (i1 => s1, i2 => cin, o => s);
end architecture str2;

---------------------------------------
--N bits 加法器:
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;

ENTITY adderN IS    GENERIC (N : integer := 16);
    PORT (a,b : IN bit_vector(N DOWNTO 1); cin: IN bit; 
        sum : OUT bit_vector(N DOWNTO 1); cout: OUT bit);
END adderN;

ARCHITECTURE structural OF adderN IS    
    COMPONENT adder
        PORT (a,b,cin: IN bit; sum, cout : OUT bit);
    END COMPONENT;  
SIGNAL carry: bit_vector(0 TO N);
BEGIN
    Carry(0) <=cin;
gen : FOR I  IN 1 TO N GENERATE
        add : adder PORT MAP (a(I),b(I),carry(I-1),sum(I),carry(I));
    END GENERATE ;
    Cout <= carry(N);
END structural;




LIBRARY ieee;
USE    ieee.electrical_systems.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY    canflash IS
port (   
        data  : out std_logic_vector(2 downto 0);
        ---- partie analogique
        quantity Vin : in real;
        quantity Vref : in real
     );
END ENTITY canflash;

ARCHITECTURE behav OF canflash IS
SIGNAL etage : std_logic_vector(7 downto 0);
BEGIN
       etage(0) <= '1' when Vin'above(Vref/8.0) else '0';
    etage(1) <= '1' when Vin'above(Vref/4.0) else '0';
    etage(2) <= '1' when Vin'above(3.0*Vref/8.0) else '0';
    etage(3) <= '1' when Vin'above(Vref/2.0) else '0';
    etage(4) <= '1' when Vin'above(5.0*Vref/8.0) else '0';
    etage(5) <= '1' when Vin'above(6.0*Vref/8.0) else '0';
    etage(6) <= '1' when Vin'above(7.0*Vref/8.0) else '0';
    etage(7) <= '1' when Vin'above(Vref) else '0';

    data <= "000" when etage = "0000000" else
            "001" when etage = "0000001" else
            "010" when etage = "0000011" else
            "011" when etage = "0000111" else
            "100" when etage = "0001111" else
            "101" when etage = "0011111" else
            "110" when etage = "0111111" else
            "111" when etage = "1111111" else
            "000";
END ARCHITECTURE behav;