1.停止forever进程
class Object;
bit kill;
task run();
fork : run_thread
wait(kill==1) disable run_thread;
forever #5ns $display("I'm still alive @ %t",$time);
join_none
endtask
endclass
// ...
Object obj;
initial begin
obj = new();
obj.run();
#1us; obj.kill = 1;
#20ns; obj = null;
#20ns; $display("End @ %t",$time);
$finish;
end
2.
typedef byte unsigned dynamic_byte_array_t[]; typedef logic fixed_logic_array_t[31:0]; dynamic_byte_array_t data; fixed_logic_array_t l_data; data = dynamic_byte_array_t'(l_data);
3.// will generate a delay of pow(2,WIDTH) clock cycles // between each change in the value of "a" `define WIDTH 20 reg [`WIDTH:0] counter; wire a = counter[`WIDTH]; always @(posedge Clk) counter <= counter + 1;
4.
SystemVerilog IEEE 1800-2012 Section 22.5.1 `define, covers text macros which can take arguments.
`define DISPLAY_MACRO1(a=1,b="A",c) $display(a,,b,,c); `DISPLAY_MACRO1(4,5,6); // Expands to $display(4,,5,,6)
Arguments can be skipped to allow the default:
`DISPLAY_MACRO1( ,5,6); // Expands to $display(1,,5,,6)
The macros can also be used to create equations
`define TOP(a,b) a + b a = `TOP(g ,h) // expanding to // a = g + h
This is not directly useful for creating variable names because it requires spaces to delimit arguments, this is where the
``
come in handy. They are used to delimit without using a space.`define MAKE_REG( width, name) reg [ width -1:0] name``_register `MAKE_REG( 4, enable) ; //should expand to // reg [ 4 -1:0] enable_register ;
5.
When you have a user-defined aggregate type in a port list, you need to put that type in a place where it will be compatible to make a connection, i.e. the module test, and the module above it that will make a connection to that port. There are two ways to accomplish this:
Pass the data type down from from a higher level using a type parameter.
module test#(type T) (input T sig); parameter A = $bits(sig.fA); parameter B = $bits(sig.fB); initial #1 $display(A,, B); endmodule module top; typedef struct { logic [3:0] fA; logic [4:0] fB; } my_t; my_t s; test #(my_t) t2(s); endmodule
displays
# 3 4
or you can put the type in a common package. However to make the struct parameterized, you need to wrap the type in a class. See section 6.25 of the 1800-2012 LRM (This is supposed to be synthesiable)
package p; class T#(int A,B); typedef struct { logic [A-1:0] fA; logic [B-1:0] fB; } my_t; endclass endpackage : p module test#(int A=1, B=2) (input p::T#(A,B)::my_t sig); initial #1 $displayb(sig.fA,, sig.fB); endmodule module top; import p::T; T#(2,3)::my_t s = '{'1, '1}; test #(2,3) t(s); endmodule
6.