以下为Verilog代码:
module led_flash(
clk,reset,led
);
input clk;
input reset;
output reg [7:0]led;
reg [25:0]counter;
always@(posedge clk or negedge reset) begin
if(!reset)begin
led<=8'd1;
counter<=0;
end
else if(counter==24999999)begin
counter<=0;
if(led==8'b1000_0000)
led<=8'd1;
else
led<=led<<1;
end
else
counter<=counter+1;
end
endmodule
以下为testbench文件
`timescale 1ns / 1ns
module led8_flash_tb();
reg clk;
reg reset;
wire [7:0]led;
led_flash u1(
.clk(clk),
.reset(reset),
.led(led)
);
initial clk=0;
always #10 clk=~clk;
initial begin
reset=0;
#201
reset=1;
#400000000
$stop;
end
endmodule