常用时序逻辑电路设计
本文主要用来存放各种时序电路代码,异步时序电路分析见另一篇文章,主要是一些跨时钟域处理电路及方法。
同步时序逻辑电路
序列检测器
从一串二进制数据中找到指定的字符串并输出信号。找“1101”,序列为16’b1110_1010_1101_0011。
状态机:
代码:
module test(
input clk,
input rst_n,
input data,
output reg y
);
localparam st0 = 2'b00;
localparam st1 = 2'b01;
localparam st2 = 2'b10;
localparam st3 = 2'b11;
reg [1:0] cur_stat;
reg [1:0] nxt_stat;
//1
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
cur_stat = st0;
else
cur_stat = nxt_stat;
end
//2
always @(*)begin
case(cur_stat)
st0:begin
if(!data)
nxt_stat = st0;
else
nxt_stat = st1;
end
st1:begin
if(!data)
nxt_stat = st0;
else
nxt_stat = st2;
end
st2:begin
if(!data)
nxt_stat = st3;
else
nxt_stat = st2;
end
st3:begin
if(!data)
nxt_stat = st0;
else
nxt_stat = st0;
end
endcase
end
//3
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
y<=1'd0;
else begin
case(cur_stat)
st0:begin
if(!data) y<=1'd0;
else y<=1'd1;
end
st1:y<=1'd0;
st2:y<=1'd0;
st3:y<=1'd0;
endcase
end
end
endmodule
testbench:
`timescale 1 ps/ 1 ps
module test_vlg_tst();
reg clk;
reg rst_n;
reg [15:0] data_t;
wire y;
wire data;
assign data = data_t[15];
test i1 (
.clk(clk),
.rst_n(rst_n),
.data(data),
.y(y)
);
initial
begin
rst_n = 0;
#50 rst_n =1;
#5000 $stop;
end
initial
begin
clk=0; forever #10 clk = ~clk;
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
data_t <= 16'b1110_1010_1101_0011;
else
data_t <= (data_t << 1);
end
endmodule
仿真结果:
最基础的同步时序电路。