HDLBits做题笔记 Verilog语法补充

Adder100i（generate-for)

题目：Create a 100-bit binary ripple-carry adder by instantiating 100 full adders.
提示：There are many full adders to instantiate. An instance array or generate statement would help here.
构建100bit的串行加法器，提示是用实例化数组及generate语句
generate语法详解.

方法一：这个方法直接把1bit的全加器融入100bit之中，没通过1bit全加器模块连接的方式，行为描述很好懂但是RTL图非常乱，通过了HDLBits，结果正确。

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );

    generate 
        genvar i;
        for (i=0;i&l