- LEF 物理库文件
- DEF 设计文件
- SDF 标准延时格式,输入最慢的SDF对Setup检查
- DCD 占空比失真Duty Cycle Distortion 。 占空比失真即时钟不对称,高电平和低电平时间发生变化。DCD会占用时间裕量(Slack)造成数字信号的失真,使过零区间偏离理想的位置。DCD通常是由信号的上升沿和下降沿之间时序不同而造成的。
- GLS 门级仿真
- DRC 设计规则检查 (from tech lef)(tech lef,工艺信息,例如线的宽度,space的大小)
- DRV (transition/fanout/cap)
- LVS 电路一致性检查 版图与电路图
- DUA 待分析设计 (backannotation),STA的反标其实是一个简单直接的过程,其中DUA中的时序弧将由SDF所指定的延迟进行标注
- GTD Global Timing Debug (GTD)
- CPF Common Power Format (CPF)
- SCM Statistical Constraint Margining
- CCD (Concurrent Clock And Data)是非常常用的一个自动调tree的option
- DFI DDR PHY Interface (DFI)
- ras row address strobe information 行
- cas column address strobe information 列地址选通
- _opad output data (同理ipad)
- _iepad input enable
- dm_ Memory data mask
- dq date queue 数据列
- dqs date queue select
- dqs/dq data strobe
- dfi_wrdata (DQ), dfi_wrdata_mask (DM), and dfi_wrdata_en (DQ/DM/DQS).When communicating with x8/x16/x32 devices, the data slice’s interface is 8 DQ/1 DM/1 DQS.
- ATB Analog Test Bus 模拟测试总线(PHY Logic to PHY IO Interface)
- Delay Line
- digital delay lines (DDL)
- std-logic,即标准单元库
- PI (PHY Independent)
- HIC :Hard Instantiated Cells硬实例化单元
- hic :Hand Instantiated Cells
- _p/_n pos-edge /neg-edge triggered flip-flop
- NCSIM 工具 Incisive simulator
- dll: delay line
- clk_phase: delayed phy clock by delay line
- clk_phase_delay: extra delayed clk_phase by another delay line in phase detect module
- CCD (clock control definition)
- PPI Pseudo-Primary Input 伪主输入
- -TI = Tie Low, +TI = Tie High