38译码器的VHDL语言实现

38译码器的VHDL语言实现

library ieee;
use ieee.std_logic_1164.all;
entity vhdl38 is
port
(
	a:in std_logic_vector(2 downto 0);
	s1,s2,s3:in std_logic;
	y:out std_logic_vector(7 downto 0)
);
end;

architecture one of vhdl38 is
begin
process(s1,s2,s3,a)
begin
	if(s1='0') then
		y<="11111111";
	elsif(s2='1' or s3='1') then
		y<="11111111";
	else
		case a is
			when "000" => y<="11111110";
			when "001" => y<="11111101";
			when "010" => y<="11111011";
			when "011" => y<="11110111";
			when "100" => y<="11101111";
			when "101" => y<="11011111";
			when "110" => y<="10111111";
			when "111" => y<="01111111";	 
		end case;
	end if;
	end process;
	end;