生成3×3的窗口
module Shift_RAM_3X3(
input clk,
input rst_n,
input per_frame_vsync,
input per_frame_href,
input per_frame_clken,
input [7:0] per_img_Y,
output matrix_frame_vsync,
output matrix_frame_href,
output matrix_frame_clken,
output reg [7:0] matrix_p11,
output reg [7:0] matrix_p12,
output reg [7:0] matrix_p13,
output reg [7:0] matrix_p21,
output reg [7:0] matrix_p22,
output reg [7:0] matrix_p23,
output reg [7:0] matrix_p31,
output reg [7:0] matrix_p32,
output reg [7:0] matrix_p33
);
wire [7:0] row1_data;
wire [7:0] row2_data;
reg [7:0] row3_data;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
row3_data <= 8'b0;
else begin
if(per_frame_clken)
row3_data <= per_img_Y;
else
row3_data <= row3_data;
end
end
Shift_RAM_3X3_8bit u1_Shift_RAM_3X3_8bit (
.D (row3_data),
.CLK (per_frame_clken & clk),
.Q (row2_data)
);
Shift_RAM_3X3_8bit u2_Shift_RAM_3X3_8bit (
.D (row2_data),
.CLK (per_frame_clken & clk),
.Q (row1_data)
);
reg [4:0]per_frame_clken_r;
reg [4:0]per_frame_vsync_r;
reg [4:0]per_frame_href_r;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
per_frame_clken_r <= 5'b0;
per_frame_vsync_r <= 5'b0;
per_frame_href_r <= 5'b0;
end
else begin
per_frame_clken_r <= {per_frame_clken_r[3:0], per_frame_clken};
per_frame_vsync_r <= {per_frame_vsync_r[3:0], per_frame_vsync};
per_frame_href_r <= {per_frame_href_r [3:0], per_frame_href};
end
end
assign matrix_frame_clken = per_frame_clken_r[4];
assign matrix_frame_href = per_frame_href_r [4];
assign matrix_frame_vsync = per_frame_vsync_r[4];
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
{matrix_p11, matrix_p12, matrix_p13} <= 24'h0;
{matrix_p21, matrix_p22, matrix_p23} <= 24'h0;
{matrix_p31, matrix_p32, matrix_p33} <= 24'h0;
end
else if(per_frame_clken_r[3])begin
{matrix_p11, matrix_p12, matrix_p13} <= {matrix_p12, matrix_p13, row1_data};
{matrix_p21, matrix_p22, matrix_p23} <= {matrix_p22, matrix_p23, row2_data};
{matrix_p31, matrix_p32, matrix_p33} <= {matrix_p32, matrix_p33, row3_data};
end
else begin
{matrix_p11, matrix_p12, matrix_p13} <= {matrix_p11, matrix_p12, matrix_p13};
{matrix_p21, matrix_p22, matrix_p23} <= {matrix_p21, matrix_p22, matrix_p23};
{matrix_p31, matrix_p32, matrix_p33} <= {matrix_p31, matrix_p32, matrix_p33};
end
end
endmodule