数字电路74LS194verilog实现

module reg74194(
  input _CR,
    input [1:0] S,
    input CP,
    input SL,
    input SR,
    input [3:0] D,
    output [3:0] Q
    );
	
	reg [3:0]q_reg=4'b0000;
	always @ (posedge CP or negedge _CR)
	begin
		if(_CR==0) q_reg<=4'b0000;
		else
			case(S)
				2'b00:q_reg<=q_reg; //keep
				2'b01:q_reg<={SR,Q[3:1]}; //rightMove
				2'b10:q_reg<={Q[2:0],SL}; //leftMove
				2'b11:q_reg<=D; //set
			endcase
	end
	assign Q=q_reg;
endmodule

测试文件

module reg74194test;

	// Inputs
	reg _CR;
	reg [1:0] S;
	reg CP;
	reg SL;
	reg SR;
	reg [3:0] D;

	// Outputs
	wire [3:0] Q;

	// Instantiate the Unit Under Test (UUT)
	reg74194 uut (
		._CR(_CR), 
		.S(S), 
		.CP(CP), 
		.SL(SL), 
		.SR(SR), 
		.D(D), 
		.Q(Q)
	);

	initial begin
		// Initialize Inputs
		_CR = 0;
		S = 0;
		CP = 0;
		SL = 0;
		SR = 0;
		D = 0;
		#4 _CR = 1;
		#4 S=2'b01;
		#4