名称:74LS194芯片设计VHDL代码及Verilog代码Quartus仿真(文末获取)
软件:Quartus
语言:Verilog,VHDL
代码功能:
1. 工程文件
2. 程序文件
完整电路代码
底层器件代码(74LS194)
3. 程序编译
整体统计报告
底层器件(74LS194)统计报告
4. RTL图
5. 仿真图
整体仿真图
LS194模块仿真图(底层器件)
部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY LS194 IS PORT ( CP : IN STD_LOGIC; CR : IN STD_LOGIC; SL : IN STD_LOGIC; SR : IN STD_LOGIC; S0 : IN STD_LOGIC; S1 : IN STD_LOGIC; D0 : IN STD_LOGIC; D1 : IN STD_LOGIC; D2 : IN STD_LOGIC; D3 : IN STD_LOGIC; Q0 : OUT STD_LOGIC; Q1 : OUT STD_LOGIC; Q2 : OUT STD_LOGIC; Q3 : OUT STD_LOGIC ); END LS194; ARCHITECTURE behave OF LS194 IS SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN S <= (S1 & S0);--合并为2bit PROCESS (CP, CR) BEGIN IF (CR = '0') THEN Q <= "0000"; ELSIF (CP'EVENT AND CP = '1') THEN CASE S IS WHEN "11" =>--置数 Q <= (D0 & D1 & D2 & D3); WHEN "01" =>--右移 Q(3) <= SR; Q(2 DOWNTO 0) <= Q(3 DOWNTO 1); WHEN "10" =>--左移 Q(0) <= SL; Q(3 DOWNTO 1) <= Q(2 DOWNTO 0); WHEN "00" =>--保持 Q <= Q; END CASE; END IF; END PROCESS;
源代码
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