题目
正确代码:
module top_module (
input clk,
input reset,
input [31:0] in,
output reg[31:0] out
);
reg[31:0] last_in; //上一次的in
reg[31:0] reset1; //使按位运算时位宽相等
assign reset1 = {32{reset}};
always @(posedge clk) begin
last_in <= in;
out <= (last_in&(~in)&(~reset1)) | (out&(~reset1));
end
endmodule
错误代码
module top_module (
input clk,
input reset,
input [31:0] in,
output reg[31:0] out
);
reg[31:0] last_in;
always @(posedge clk) begin
last_in <= in;
out <= (last_in&(~in)&(~reset)) | (out&(~reset));
end
endmodule
错误原因:reset按位运算时位宽不匹配