Exams/ece241 2013 q4
其中例题在对dfr描述的时候用的是S的状态,我们使用FR的状态对dfr状态进行改变。
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
reg [2:0] c_state,n_state;
// parameter t1=2’b00,t2=2’b01,t3=2’b10,t4=2’b11;
always @(posedge clk)
begin
if(reset)
c_state<=4’b111;
else
c_state<=n_state;
end
always @(*)
begin
case(s)
3’b000:n_state<=3’b111;
3’b001:n_state<=3’b011;
3’b011:n_state<=3’b001;
3’b111:n_state<=3’b000;
default:n_state<=3’b111;
endcase
end
assign {fr3,fr2,fr1}=c_state;
always @(posedge clk)
begin
if(reset)
dfr<=1;
else
begin
if(c_state>n_state)
dfr<=0;
else if (c_state<n_state)//用fr状态进行比较的
dfr<=1;
else
dfr<=dfr;
end
end
endmodule