层次化设计_全加器

1.原理

2.代码

2.1  full_adder.v

module full_adder
(
	input  wire 	in_1  ,
	input  wire     in_2  ,
	input  wire     cin  ,
	
	output wire     sum		,
	output wire     count	
);

wire b0_sum;
wire b0_count;
wire b1_count;


half_adder half_adder_inst0
(
	.in_1 (in_1),
    .in_2 (in_2),
  
    .sum  (b0_sum),
    .count(b0_count)
);


half_adder half_adder_inst1
(
	.in_1 (cin),
    .in_2 (b0_sum),
  
    .sum  (sum),
    .count(b1_count)
);

assign count=(b0_count | b1_count);

endmodule

2.2 tb_full_adder.v

`timescale 1ns/1ns
module tb_full_adder();

reg in_1;
reg in_2;
reg cin;

wire sum;
wire count;

initial
	begin
		in_1<=0;
		in_2<=0;
		cin<=0;
	end
	
initial 
   begin
	$timeformat(-9,0,"ns",6);
	$monitor("@time %t:in_1=%b,in_2=%b,cin=%b,sum=%b,count=%b",$time,in_1,in_2,cin,sum,count);
	end
	
always#10 in_1 <= {$random}%2;
always#10 in_2 <= {$random}%2;
always#10 cin <= {$random}%2;

full_adder full_adder_inst0
(
	.in_1 	 (in_1),
    .in_2    (in_2),
    .cin     (cin),
			
    .sum	 (sum),
    .count   (count)
);

endmodule