设计16位二选一的选择器
选择控制端 s | 输出端x |
---|---|
0 | a |
1 | b |
要求如下:
- 编写VHDL代码
代码如下:
-- 十六位二选一的选择器
library ieee;
use ieee.std_logic_1164.all;
entity one_mux2_16 is
port(a, b: in std_logic_vector(15 downto 0);
s: in std_logic;
f_linxuan: out std_logic_vector(15 downto 0));
end one_mux2_16;
architecture behave of one_mux2_16 is
begin
process(a, b, s)
begin
if s = '0' then
f_linxuan<= a;
else
f_linxuan<= b;
end if;
end process;
end behave;