VHDL——全加器的实现（元件例化）

1.逻辑电路

2.VHDL语言

2.1半加器h_adder1的实现

library ieee;
use ieee.std_logic_1164.all;

entity h_adder1 is    
	port (a,b:in STD_LOGIC;
		   co,so:out STD_LOGIC);
end h_adder1;

architecture fh of h_adder1 is
begin
  so <= not(a xor (not b));
  co <= a and b;
end fh;

2.2实现或门

library ieee;
use ieee.std_logic_1164.all;

entity or2a is
  port(a,b:in std_logic;
    c:out std_logic);
end or2a;

architecture one of or2a is
begin
  c <= a or b;
end one;

2.3实现全加器

library ieee;
use ieee.std_logic_1164.all;

entity f_adder is    
	port (ain,bin,cin:in std_logic;
			cout,sum :out std_logic);
	end entity f_adder;
architecture fd1 of f_adder is
	component h_adder1                 --调用h_adder1模块，必须声明此模块的端口
	  port（a,b : in std_logic;
	       co,so : out std_logic）;
	end component;
	component or2a                     --调用或门模块
		port(a,b: in STD_LOGIC;
			   c:out STD_LOGIC);
	end component; 
   signal d,e,f: std_logic;
begin
  u1 : h_adder1 port map(a => ain , b => bin , co => d , so => e);   --元件例化
  u2 : h_adder1 port map(a => e , b => cin , co => f , so => sum);
  u3 : or2a port map(a => d , b => f , c => cout);
end architecture fd1;