一个时钟频率检测模块模块的verilog程序分享:
功能说明:检测时钟频率
使用的编辑器:Notepad++
顶层接口说明:如下图
verilog程序源码:
module clk_freq_check(
input wire i_clk_100mhz, // 100Mhz时钟
input wire i_check_clk, // 被检测时钟
output reg [31:0] o_check_clk_freq = 32'd0 // 被检测时钟频率, 单位: Hz
);
parameter time_1s = 100_000_000;
parameter time_500ms = 50_000_000;
reg [31:0] time_100mhz_cnt = 32'd0;
reg time_sig = 1'b0;
wire time_sig_sync;
reg [1:0] time_sig_sync_r;
reg [31:0] time_check_cnt = 32'd0;
always @ ( posedge i_clk_100mhz ) begin
if ( time_100mhz_cnt >= ( time_1s - 1'b1 ) ) begin
time_100mhz_cnt <= 32'd0;
end else begin
time_100mhz_cnt <= time_100mhz_cnt + 1'b1;
end
end
always @ ( posedge i_clk_100mhz ) begin
time_sig <= ( time_100mhz_cnt < time_500ms );
end
xpm_cdc_single #(
.DEST_SYNC_FF ( 2 ), // integer; range: 2-10
.SIM_ASSERT_CHK ( 0 ), // integer; 0=disable simulation messages, 1=enable simulation messages
.SRC_INPUT_REG ( 1 ) // integer; 0=do not register input, 1=register input
) u_xpm_cdc_single(
.src_clk ( i_clk_100mhz ), // optional; required when SRC_INPUT_REG = 1
.src_in ( time_sig ),
.dest_clk ( i_check_clk ),
.dest_out ( time_sig_sync )
);
always @ ( posedge i_check_clk ) begin
time_sig_sync_r <= { time_sig_sync_r[0], time_sig_sync };
end
always @ ( posedge i_check_clk ) begin
if ( time_sig_sync_r == 2'b01 ) begin
time_check_cnt <= 32'd0;
end else begin
time_check_cnt <= time_check_cnt + 1'b1;
end
end
always @ ( posedge i_check_clk ) begin
if ( time_sig_sync_r == 2'b01 ) begin
o_check_clk_freq <= time_check_cnt;
end else begin
o_check_clk_freq <= o_check_clk_freq;
end
end