//cr_tb.sv文件内容
`include "cr.vh"
//宏定义
`define CLK_MAIN_IDX `h00
`define CLK_DDRIDX `h01
`define CLK_DDR0_IDX `h02
...
module cr_tb
assign clk_array = {
clk_main,
clk_core_l2c_0,
clk_ddr0,
...
test_o
};
initial begin: main_block
...
set_ddr0_feq;//调用task
...
end
task set_ddr0_freq;
get_real_clock(`CLK_DDR0_IDX,duration);
$display("freq of clk_ddr0 is %f", duration);
endtask
task get_real_clock;
input int index;
output real_clock;
real stime, duration;
@(posedge clk_array[index]);
stime = $realtime;
@(negedge clk_array[index]);
duration = $realtime - stime;
real_clock =500.0/duration;
endtask
endmodule
测试多时钟频率-systemVerilog
最新推荐文章于 2023-03-21 17:35:57 发布