Linux iverilog编译与波形显示

## 命令
iverilog *.v
vvp a.out
gtkwave reg.vcd

initial began

$finish;

end

//仿真文件必须加入 生成波形文件

initial
    begin            
        $dumpfile("test_tb.lxt");
        $dumpfile("reg.vcd");
        $dumpvars(0, test_tb);
    end 

终端显示

blue@orange:~/文档/verilog/verilog-test$ ls
test_tb.v  test.v
blue@orange:~/文档/verilog/verilog-test$ iverilog *.v
blue@orange:~/文档/verilog/verilog-test$ ls
a.out  test_tb.v  test.v
blue@orange:~/文档/verilog/verilog-test$ vvp a.out 
VCD warning: test_tb.v:25: Overriding dump file test_tb.lxt with reg.vcd.
VCD info: dumpfile reg.vcd opened for output.
blue@orange:~/文档/verilog/verilog-test$ ls
a.out  reg.vcd  test_tb.v  test.v
blue@orange:~/文档/verilog/verilog-test$ gtkwave reg.vcd