generate用法

verilog2001中在呢个价四个关键字，generate，endgenerate, genvar, localparam.

genvar是一个新增的数据类型，用在generate的循环中的标尺变量必须定义为genvar类型。

 module buffer_1(
     input    wire    in,
     output   wire    out
 );
  
assign out = ~in;
endmodule

  module buffer_8(
      input    wire[7:0] din,
      output   wire[7:0] dout
  );
      
 genvar i;
 generate
         for(i=0; i<8; i=i+1) begin
             buffer_1 buffer_1_1(.in(din[i]), .out(dout[i]));
        end
endgenerate
endmodule

generate 语句中可以出现以下三种语句：

1. 循环 for
2. 条件if else
3. 分支case

循环

module nbit_xor
 #(parameter SIZE=16)
 (input(SIZE-1:0) a,b,output[SIZE-1:0] y);
 genvar gv_i;
 generate
    for(gv_i=0;gv_i<SIZE;gv_i++)
	  begin:sblka
	       xor uxor(y[gv_i],a[gv_i],b[gv_i]);
	  end
 endgenerate
endmodule

条件

module adder
 #(parameter SIZE=4)
 (input[SIZE-1:0] a,b,
  output[SIZE-1:0] sum,
  output carry_out);
  wire [SIZE-1:0] carry;
  
  genvar gv_k;
  generate
    for(gv_k=0;gv_k<SIZE;gv_k++)
	   begin: gen_blk_adder
	      if(gv_k == 0)
		     half_adder u_ha (.a(a[gv_k]),
			                  .b(b[gv_k]),
							  .sum(sum[gv_k]),
							  .carry_out(carry[gv_k]),
							  );
		  else
		     full_adder u_ha (.a(a[gv_k]),
			                  .b(b[gv_k]),
							  .sum(sum[gv_k]),
							  .carry_in(carry[gv_k-1]),
							  .carry_out(carry[gv_k]),
							  );
	   end
  endgenerate
endmodule 

分支

module adder
 #(parameter SIZE=4
   parameter IMPLEMENTATION_LEVEL=0)
 (input[SIZE-1:0] arg1,arg2,
  output[SIZE-1:0] result,
  );
  
  generate
    case(IMPLEMENTATION_LEVEL)
       0: assign result=arg1+arg2;
	   1:.....;
	   2:.....;
	   3:.....;
	   default:......;
  endgenerate
endmodule